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Torrent Technical Documents


General Documentation

Torrent Data Sheet [1] Rev 4.1
TRNT-AD-11-0001 Torrent DHE Architecture [2] Rev 5.0
TRNT-AD-11-0001 Torrent Performance Requirements [3] Rev 0.0
TRNT-AD-04-0001 Torrent DHE Compliance Tests [4] Rev 2.5
TRNT-AD-04-0002 Report on Torrent DHE Compliance Tests [5] Rev 1.0

Torrent DHE Interface Control Documents

The DHE is what is generically called a controller. This interface level is governed by the MONSOON Interface Control Documents (ICD) level 7 and 8. These documents control the hardware interfaces of the system.

Torrent  - ICD 7.? TRNT-AD-01-0001 AFE-CCD Circuit Board Dimensions [6] Rev -OD-
Torrent  - ICD 7.3 TRNT-AD-01-0003 Torrent DHE LCB to AFE Interface Description [7] Rev 0.0
Torrent  - ICD 7.4 TRNT-AD-01-0004 Torrent DHE PSM to LCB Interface Description [8] Rev 0.0
Torrent  - ICD 7.6 TRNT-AD-01-0006 Torrent DHE PSM to TSM Interface Description [9] Rev 0.0

System Configuration User Questionair

Torrent User Survey [10] Rev 4 - Used to specify the details of a buildable configuration for a Torrent DHE

Documentation Index

TRNT-AD-10-0001 Master Documentation List [11] Rev 0

Torrent Hardware

The relationship between the various hardware modules of the Torrent DHE is shown here [12] in the DHE interconnect diagram.

The controlled grounding scheme for the Torrent DHE can be found here [13]

Torrent DHE Hardware Description Guide - Covers all Torrent electronics.
TRNT-AD-08-0007 DHE Hardware Description [14] Rev 1.1

The pages below provide access to the schematic and assembly information of the Torrent hardware modules.

The information on these pages is generally arranged as:

Assembly drawings
Schematic diagrams
Layout packages
Bill of materials
Firmware loader products
Testing Procedures

Note that to use this information for your own purposes (i.e. build it or use it as the basis of a new design) you must agree to the open source license agreement. The license terms can be found here [15].

Local Control Board (LCB)

Local Control Board
TRNT-EL-04-0002 LCB Top Assembly [16] Rev -B-
TRNT-EL-04-1002 LCB Fabrication Detail [17] Rev -B-
TRNT-EL-04-2002 LCB Schematic Diagram [18] Rev -B-
TRNT-EL-04-3002 LCB Layout Package [19] Rev -B-
TRNT-EL-04-4002 LCB Bill of Materials [20] Rev -B-

Firmware Loader Products

TRNT-EL-06-0001 LCB FPGA - Fpga Loader [21] Rev 2.22 (torrentfpga_ver222.bit)
TRNT-EL-06-0001 LCB FPGA - EEprom Loader [22] Rev 2.22 (torrentfpga_ver222.mcs)

LCB Testing Procedures
TRNT-TS-01-0003 LCB Test Procedure [23] Rev 0

Local Control Board Mezzanine (LCB-MEZ)

TRNT-EL-04-0003 LCB-MEZ Top Assembly [24] Rev -A3-
TRNT-EL-04-1003 LCB-MEZ Fabrication Detail [25] Rev -A-
TRNT-EL-04-2003 LCB-MEZ Schematic Diagram [26] Rev -A4-
TRNT-EL-04-3003 LCB-MEZ Layout [27] Rev -A-
TRNT-EL-04-3003 LCB-MEZ Layout Package [27] Rev -A-
TRNT-EL-04-4003 LCB-MEZ Bill of Materials [28] Rev -A5-

Power Supply Module (PSM)

TRNT-EL-04-0001 PSM Top Assembly [29] Rev -B-
TRNT-EL-04-1001 PSM Fabrication Detail [30] Rev -B-
TRNT-EL-04-2001 PSM Schematic Diagram [31] Rev -B-
TRNT-EL-04-3001 PSM Layout Package [32] Rev -B-
TRNT-EL-04-4001 PSM Bill of Materials [33] Rev -B-

CCD Analog Front End (AFE)

CCD Analog Front End
TRNT-EL-04-0004 AFE-CCD Top Assembly [34] Rev -C-
TRNT-EL-04-1004 AFE-CCD Fabrication Detail [35] Rev -C-
TRNT-EL-04-2004 AFE-CCD Schematic Diagram [36] Rev -C1-
TRNT-EL-04-3004 AFE-CCD Layout [37] Rev -C1-
TRNT-EL-04-4004 AFE-CCD Bill of Materials [38] Rev -C1-

Analog Front End Calibration Worksheet
AFE-CCD Calibration Worksheet [39]

Analog Front End Extender Board
TRNT-EL-04-0008 AFE-EXT Circuit Board Dimensions [40] Rev -OD-
TRNT-EL-04-1008 AFE-EXT Fabrication Detail [41] Rev -OD-
TRNT-EL-04-2008 AFE-EXT Schematic Diagram [42] Rev -0D-
TRNT-EL-04-3008 AFE-EXT Layout [43] Rev -OD-

Analog Front End Testing Procedures
TRNT-TS-01-0004 AFE-CCD Test Procedure [44] Rev 0

Transition Module (TSM)

Transition Module Preamplifier for CCD (TSM-CCD)

TRNT-EL-04-0007 TSM-CCD Top Assembly [45] Rev -C1-
TRNT-EL-04-1007 TSM-CCD Fabrication Detail [46] Rev -C-
TRNT-EL-04-2007 TSM-CCD Schematic Diagram [47] Rev -C1-
TRNT-EL-04-4007 TSM-CCD Bill of Materials [48] Rev -C1-

TRNT-EL-04-0007 TSM-CCD Top Assembly [49] Rev -B-
TRNT-EL-04-1007 TSM-CCD Fabrication Detail [50] Rev -B-
TRNT-EL-04-2007 TSM-CCD Schematic Diagram [51] Rev -B-
TRNT-EL-04-3007 TSM-CCD Layout [52] Rev -B-
TRNT-EL-04-4007 TSM-CCD Bill of Materials [53] Rev -B-

Transition Module Utility Board (TSM-UTIL)
TRNT-EL-04-0009 TSM-UTIL Top Assembly [54] Rev -A1-
TRNT-EL-04-1009 TSM-UTIL Fabrication Detail [55] Rev -A-
TRNT-EL-04-2009 TSM-UTIL Schematic Diagram [56] Rev -A2-
TRNT-EL-04-3009 TSM-UTIL Layout [57] Rev -A-
TRNT-EL-04-3009 TSM-UTIL Layout Package [58] Rev -A-
TRNT-EL-04-4009 TSM-UTIL Bill of Materials [59] Rev -A4-

Transition Module Utility Board Testing Procedures
TRNT-TS-01-0005 TSM-UTIL Test Procedure [60] Rev 0

CCD Flex Circuits (CCD-FLEX)

Video Flex
TRNT-EL-04-0005 CCD-FLEX-VID Top Assembly [61] Rev -A-
TRNT-EL-04-1005 CCD-FLEX- [62]VID [61] Fabrication Detail [62] Rev -A-
TRNT-EL-04-2005 CCD-FLEX- [63]VID [61] Schematic Diagram [63] Rev -A-
TRNT-EL-04-3005 CCD-FLEX- [64]VID [61] Layout Package [64] Rev -A-

Clock and Bias Flex
TRNT-EL-04-0006 CCD-FLEX-CB Top Assembly [65] Rev -A-
TRNT-EL-04-1006 CCD-FLEX-CB Fabrication Detail [66] Rev -A-
TRNT-EL-04-2006 CCD-FLEX- [67]CB [65] Schematic Diagram [67] Rev -A-
TRNT-EL-04-3006 CCD-FLEX- [68]CB [65] Layout [68] Rev -A-

Cables

TRNT-EL-03-0001 CBL PSM to TSM-UTIL Connector [69]
TRNT-EL-03-0002 CBL TSM-UTIL to Shutter and Preflash Connector [70]
TRNT-EL-03-0003 CBL GIGe Ethernet Shield Wire [71]
TRNT-EL-03-0006 CBL TSM Chassis Ground Wire [72]

Torrent Software

MONSOON/Torrent Software Setup Guide
MNSN-AD-08-0005 MONSOON Software Setup Guide [73] Rev 2.1

Torrent Software Description
TRNT-AD-08-0001 Torrent Software System Description [74] Rev 0

Acquisition Software Client
TRNT-AD-08-0002 borg and mborg clients [75] Rev 0

System Configuration Tools
TRNT-AD-08-0006 Software User Manual [76] Rev 0

Attribute Extraction Tool
TRNT-AD-08-0003 Assimilate [77] Rev 1.2

Attribute Collector Tool
TRNT-AD-08-0004 Collector [78] Rev 1.1

Torrent Sequencer description
TRNT-AD-08-0012 Torrent Sequencer Description [79] Rev 0

Sequencer Assembler
Torrent assembler [80] Rev 6.0

Calibration eeprom format information

Calibration EEPROM Description

The calibration EEPROMs for Torrent systems are contained on each of the component electronics boards. A fully populated Torrent system will have five Calibration EEPROMs, four in the Controller box and one in the TSM box. There is one EEPROM on the LCB, one on the PSM and one on each of the AFE boards.

These EEPROMs are currents arranged as 128 pages of 16 words each 32 bits wide. Pages 0 and 1 are ID pages that contain information to identify and help verify the data stored in the EEPROM.

Data stored in the EEPROMS is all integer values. Where a floating point value is desired we store the value as int( value * 1000 ) This limits the range of values that can be stored to -2,147,483.000 to 2,147,483.000. We could not think of any requirement that required a greater range

A copy of the data in the EEPROMs for each system is kept in a set of EEPROM Mirror Files stored in the $MONSOON_CFG/_sysName configuration directory for the system. Changing out a DHE Controller will require obtaining the correct mirror files for the new controller from the Torrent configuration database

EEPROM ID Page 0 Structure

EEPROM Page 0 Layout
Word # Word Name Board Default Value Long Name Comments
0 PSTORFORMAT ALL 0x00000001 EEPROM Storage Format The Code for the Format of the data stored in this EEPROM (1)
1 MDLIDCODE LCB 0x00000010 Module ID Code The code number assigned to the LCB boards (16)
    PSM 0x00000020   The code number assigned to the PSM boards (32)
    CCD AFE 0x00000040   The code number assigned to the CCD AFE boards (64)
    IR AFE 0x00000050   The code number assigned to the IR AFE boards (80)
    TSM Utility 0x00000030   The code number assigned to the IR AFE boards (48)
2 MDLVARCODE ALL 0x00000001 Module Variant Code The Variant ## of a board that differs from a standard board (1)
3 MDLREVNUM ALL 0x00000001 Module Release Number The release number for the module being read all still at release 1
4 MDLSERNUM ALL 0x0000xxxx Module Serial number The serial number of this board. Currently not in use
5 SYSFPGACODE ALL 0x000000CC System FPGA Code Version The FPGA code version used to write this EEPROM Currently 204
6 - 15 Not Used ALL 0x00000000 Not Used Locations Reserved

 

EEPROM ID Page 1 Structure

EEPROM Page 1 Layout
Word # Word Name Board Default Value Long Name Comments
0 MDLLASTTESTDATE ALL 20090316 Module's Last Test Date The date of the last time this board was tested (various)
1 LASTWRTDATE ALL 20110318 EEPROM Last Written Date The date of the last time this EEPROM was written (various)
2 VLDPAGECNT ALL 0x00000005 Valid Page Count The number of pages in the EEPROM that contain Valid Data (various)
3 - 11 Not Used ALL 0x00000000 Not Used Locations Reserved
12 - 15 CRC0 - CRC3 ALL 7FE163FB6 CRC code portion 0 - 3 The 128 byte representation of the MD5Sum calculated on the Data in all valid pages excepting Page 1 words 12 through 15 (various)

Setting up a System Configuration Data Set

Setting up a system configuration data set

This is a basic guide to setting up a system configuration from scratch ...

In big-boy

1. run bldMNSN

  to setup distribution directory structure

2. run assimilate -version 207 -sysName mySystemName

  -version points to the version of firmware that is in the hardware
  -sysName points to a common directory of form 
  /MNSN/soft_dev/cfg/_mySystemName/.dscFiles and
  /MNSN/soft_dev/cfg/_mySystemName/.eep
  which are used to contain the Torrent specific configuration files

3. run arrayDesc -type genericdetectorType -arrayID thisDetectorName -fpName mySystemName for as many detectors that make up the focal plane, changing the -arrayID value for each one.

  -type identifies a generic detector description
     currently available types are 
        e2v44-82
        e2v231-84
        lbnl234
        STA1042
  -arrayID is the unique identifier for this detector, usually the serial number or a positional key
  -fpName is the system configuration name

Format of attributes set by the sysName.ini file created by collector

see file big-boy:/MNSN/soft_dev/Torrent_Text/sysName.ini.tmplt

The values in the template file will be replaced by the "collector" with values read from the system TSM eeprom

Format of attributes set by the sysName_DefaultSetup.mod file created by collector

see file big-boy:/MNSN/soft_dev/Torrent_Text/sysName_DefaultSetup.mod.tmplt

The values in the template file will be replaced by the "collector" with values read from the system TSM eeprom.

Standard Definitions for Sequencer Code

User Interface, PAN Code and Sequencer Handling for Regions of Interest (ROI) readout

Reading out Regions of Interest (ROI) for CCD focal planes can be extremely complex. The inter-connection between number of outputs per detector, number and orientation of detectors and pixel binning can result in scenarios that are too complex for the simple sequencer processing available in MONSOON/Torrent systems.

Four user attributes are used to describe a region of interest. These attributes are all described by pixel positions or counts given assuming no binning is being done. The values loaded down to the sequencer are modified to take into account any requested binning values.

  • roiRow - This attribute gives the starting row of the ROI in unbinned rows
  • roiCol - This attribute gives the starting column of the ROI in unbinned pixels
  • roiRSize - this is the size of the requested ROI in unbinned rows
  • roiCsize - this is the size of the requested ROI in unbinned columns.

The following explains the restrictions on ROI definitions made to simplify ROI handling to prevent some of this complication.

  1. Only ONE ROI may defined for any single integration. - This results from a basic assumption made by the System that ROI readout is done for the purpose of reducing the time required to readout the focal plane, either to capture transient events or to reduce the signal level on bright objects.
  2. The data provided during ROI readout will be symmetric WRT the CCD output configuration. - This means that for a CCD with more than one output the amount of data may be more than requested and may include extra or ghost ROIs for other parts of the CCD.
  3. In a multi-detector focal plane, the ROI will be described by coordinates on a single CCD. - The data provided will include that ROI from all detectors in the Focal plane.
  4. In the case where a requested ROI extends past a CCD output boundary the ROI will be redefined to be symmetrical about the output boundary. - e.g. a single 2048 Column by 4096 Row detector is being read out from two outputs in the AB configuration (outputs in the lower left and lower right corners). A ROI definition of

    roiRow=300, roiCol=300, roiRsize=500, roiCsize=1000; will result in the ROI extending past the 1024 output boundary. The ROI will be redefined to:
    roiRow=300, roiCol=300, roiRsize=500, roiCsize=724; which will result in the user getting the requested data but also getting 448 columns from the B output that were not requested.
  5. The PAN saver software will send the DHS only the data provided by the DHE. In addition the standard position size description for the data will contain the finished position and size of the ROI. IT is the responsibility of the user interface software to inform the DHS of the requested position ans size of the ROI.
  6. I'm sure there should be more but I won't know till the code is done WATCH THIS SPACE..

 

uCode Standard Loop Register Usage Guidelines

There are sixteen 16-bit loop registers for available in the Sequencer to enable code flow control. The table below shows their current default usage. While these registers are general purpose loop registers using them for other than their reserved purpose will require the writing of a custom Detector library routine (detCalcPixels) to load the registers with correct values before taking an image.

The generic_CCD and basciCCD detector libraries use these assignments, but load the seqColBin register with one less than the requested number of pixels to be binned and sets the user Bit serBinEnbl to 1 if serial binning is active. The chileCCD detector library uses these assignments, and loads the seqColBin register with the requested number of pixels to be binned and does not use serBinEnbl user bit.

Standard Loop Register Usage
Register number FPGA Register name CCD User Register name CCD Sequencer Usage IR User Register name IR Sequencer Usage Comments
0 SeqLoopReg[0] seqRowCount #NROW seqRowCount #ROW_CNT Number of rows to readout i.e. for CCDs the number of parallel or slow shifts
1 SeqLoopReg[1] seqColCount #NCOL seqColCount #COL_CNT Number of columns to readout i.e. for CCDs the number of serial or fast shifts
2 SeqLoopReg[2] seqRowBin #NPBINS seqFSamples #FSAMPLES Number of rows to bin during CCD readout or number of Fowler samples in IR Readout
3 SeqLoopReg[3] seqColBin #NSBINS seqDigAvg #DIG_AVG Number of columns to bin during CCD readout or number of Digital Average samples in IR Readout
4 SeqLoopReg[4] seqRoiRow #ROIROW seqCoAdds #COADDS Number of rows to skip during CCD ROI readout or number of Co-Adds in IR Readout
5 SeqLoopReg[5] seqRoiCol #ROICOL seqLoopDly #LOOP_DLY Number of columns to skip during CCD ROI readout or read loop delay factor in Fowler IR Readout
6 SeqLoopReg[6] seqRoiRskip #RROWSKP seqSweeps #SWEEPS Number of rows to skip after ROI readout is Complete or number of reset cycles before integration in IR mode
7 SeqLoopReg[7] seqRoiCskip #RCOLSKP seqSyncResets #SYNC_RESETS Number of columns to skip on each row after the ROI columns are read out or number of resets to do when syncing two DHE's
8 SeqLoopReg[8] seqFocusShft #FOCUS_SHFT seqRstTime #RST_TIME number of rows to shift image between focus exposures
9 SeqLoopReg[9] seqPreScan #XPRE Not Assigned Not Assigned number of prescan pixels to read (Usually not converted or transferred to the PAN
10 SeqLoopReg[10] seqShtrDly #SHUTDLY Not Assigned Not Assigned The time in ms to delay while the shutter opens or closes if these times are different use an unassigned register for the closing time.
11 SeqLoopReg[11] OvrScanRowCnt #OSROWCNT Not Assigned Not Assigned Number of binned rows to convert after reading ROI rows and skipping unread active rows
12 SeqLoopReg[12] OvrScanColCnt #OSCOLCNT Not Assigned Not Assigned Number of binned pixels to convert after reading ROI pixels skipping unread active pixels
13 SeqLoopReg[13] Not Assigned Not Assigned Not Assigned  
14 SeqLoopReg[14] Not Assigned Not Assigned Not Assigned  
15 SeqLoopReg[15] Not Assigned Not Assigned Not Assigned  

uCode Standard User Bit Usage Guidelines

The MONSOON/Torrent systems have in the sequencer Control register four user settable bits that can be used with The conditional jump instruction to steer the ucode execution. The following are the current default usage for these bits.

Standard SeqUserBits Usage
User bit number FPGA Attribute name CCD User Attribute name CCD Sequencer Usage IR User Attribute name IR Sequencer Usage Comments
0 SeqUserBit0 seqContRun #CONT_RUN seqContRun #CONT_RUN Debug function - run process indefinitely after start exposure received
1 SeqUserBit1 serBinEnbl #SBIN_ENB Not Assigned #IDLERST_ENBL Enable serial binning in CCD readout or enable array resets during idle time for IR apps.
2 SeqUserBit2 rdRoiEnbl #RDROI_ENB digAvgEnb #DIGAVG_ENBL Tells the sequencer a ROI readout is in progress for CCDs or enable digital averaging in IR apps.
3 SeqUserBit3 Not Assigned Not Assigned Not Assigned #ROWRST_ENBL Enable Row Reset mode in IR apps.

 

Torrent Firmware

Firmware Description Documents

TRNT-AD-08-0010 Firmware Users Guide for Version 2.22 [81] Rev 2
TRNT-AD-08-0011 AFE Control Module Firmware Guide [82] Rev 0 - Needs updating !

Firmware Design Guides

Firmware Design Outline Torrent LCB Firmware Design [83] Rev -C3-
From Open-Cores. Wishbone Bus specification [84] Rev -B3-1-
Clock Generator Device Programming Clock Generation Workbook [85] Rev 4
AFE Serial device data format description Torrent Serial Device Control List [86]
Power Supply to Pixel Sychronization Power Supply Sync Analysis [87]

Firmware Sources

System Level
TRNT-EL-06-0001 TorrentFpga_Ver222 [88]

Module Level
AFE_Control_Ver221 [89]
CFG_Services_Ver220 [90]
CLK_Services_Ver221 [91]
DummyModule_Ver220 [92]
LCB_Control_Ver222 [93]
PIX_Services_Ver221 [94]
PSM_Services_Ver221 [95]

Templates
CmdDecodeFifo [96]
CommsDemuxPixBuffr_V106 [97]
I2C_InterfaceV100 [98]
I2C_Inerface_Ver210 [99]
PixDataMuxFifo_V103 [100]
SeqPatMemCore [101]
SeqProgMemCore [102]
SerialFPDP_fifo_5v5 [103]
SerialFPDPV5v5a - Contact Peter Moore (pmoore_at_noao.edu)
SerialFPDPV5V5b - Contact Peter Moore (pmoore_at_noao.edu)
SyncPortFifo_V100 [104]
Uart_8 [105]
UartFifo [106]
VideoFifo [107]
WishBoneIntercon_Ver222 [108]
WishBoneMasterInterfaceV106 [109]
WishBoneSlaveInterface_Ver207 [110]
NOAO_tblock [111]

Firmware Information - Quick Links


DHE Communication link bandwidths

There are four communication channels available on the Torrent DHE. The table below shows the available bandwidth for these links and their intended use.

DHE Communication Channels
Channel Bit Rate Command Bandwith (32-bit Words) Video Data Bandwith (18-bit Words) Purpose
Systran 1.0625 GBit/sec 26.5 Meg/sec 26.5 (53 for 16-bit packed pixels) Meg/sec Primary command downlink, Primary data uplink.
Sync In/Out 39.8 Meg/sec 1.0 Meg/sec n/a Inter-DHE communications, commands, synchronization
UART 9600 240 / sec n/a Engineering and maintenance
GIGe Vision Gigabit Ethernet 412.5 K/sec 26.5 Meg/sec (16-bit words). Alternate control downlink and data uplink

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LCB Clock Sources and Frequencies

There are several clock sources available from the LCB clock synthesizer hardware (U28). These clocks provide synchronization to specific areas of the Torrent hardware and firmware. The table below lists the clock name, the nominal frequency and their intended application.

Available LCB clock sources
Clock Name Frequency (Mhz) Purpose
OCLK (internal) 106.25 LCB Oscillator used during LCB Initialization and in Master mode.
sync_in_clk (internal) 39.84375 Master clock input when in Slave mode. OCLK is shut down
BCLK (internal) 106.25 (Master) / 39.84375 (Slave) Clock source for the clock synthesizer. OCLK or sync_in_clk
SysClk (internal) 106.25 General logic, Wishbone bus clock
LCLK 106.25 Low jitter clock source for the GTP Transceiver (SFPDP comms)
PCLK 159.375 Memory.
DCLK 79.6875 AFE interface bridge logic.
TCLK 39.84375 AFE ADC data clock
MCLK 39.84375 Sync port communications and synchronization logic

These clocks are derived from U28 (LMK03000) using the following register constants

LMK03000 Programming Scheme for Master DHE (BCLK = 106.25 MHz)
Clock Name Phase detect Freq. (Mhz) VCO Freq. (Mhz) Divide by 'R' Value VCO Divider Value Divide by 'N' Value Clock Divider Value
SysClk 13.28125 1275 8 2 48 6
LCLK 13.28125 1275 8 2 48 6
PCLK 13.28125 1275 8 2 48 4
DCLK 13.28125 1275 8 2 48 8
TCLK 13.28125 1275 8 2 48 16
MCLK 13.28125 1275 8 2 48 16

For DHE Slave operation, where the BCLK frequency is 39.84375 MHz, the value of the Divide by 'R' value changes to 3. All other constants remain the same.

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Clock Sources for Master sync clock

There are two clock sources available to provide the master OUTSYNC_CLK. The FPGA internally generated source and a source generated directly from the clock synthesizer hardware (U28). These clocks provide synchronization to the slave DHE systems. The table below lists the combinations available by writing to the SyncClkSelect attribute.

SYNC clock sources and routing
Attribute value OUTSYNC_CLK Source FPGA SYNC CLK source Attribute value OUTSYNC_CLK Source FPGA SYNC CLK source
0x0 U28 U28 0x8 Invalid state Invalid state
0x1 FPGA U28 0x9 Invalid state Invalid state
0x2 U28 FPGA 0xA U28 Disabled
0x3 FPGA FPGA 0xB FPGA Disabled
0x4 Disabled U28 0xC Disabled Disabled
0x5 Invalid state Invalid state 0xD Invalid state Invalid state
0x6 Disabled FPGA 0xE Invalid state Invalid state
0x7 Invalid state Invalid state 0xF Invalid state Invalid state

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RS232 Communication Channel Command Codes

The LCB supports an engineering RS232 communication port for engineering use. The available commands (shown below) are prefixed with the 'plus' (+) character (0x2B) and completed with a 'Line Feed' character (0x0A). The standard format of 9600 Baud, 8 bits, no parity is supported. Upper or lower case characters are recognized. All address and data values must be expressed in hex. Fields must be separated by a space or tab character. Backspace clears the current command (although currently the display looks messy).

Torrent engineering commands for RS232 link
First Field Second Field Third Field Forth Field Command description
+A 16-bit vector (valid range 0x0 through 0xFFFF) Not Used Not used Forces an Asynchronous Command to synchronize the communication channels after reset
+R Module number (valid range 0x01 through 0xFF) Module Address (valid range 0x0 through 0xFFFF) Not used Returns the 32-bit contents of the addressed register (in hex)
+W Module number (valid range 0x01 through 0xFF) Module address (valid range 0x0 through 0xFFFF) 32-bit data value (valid range 0x0 through 0xFFFFFFFF) Writes the 32-bit value to the addressed register
+S 8-bit data value (valid range 0x0 through 0xFF) as sequencer start vector Not used Not used Triggers a 'Start Exposure' event in the sequencer with the 8-bit start vector

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Firmware Module Addressing and Identity Codes

As per ICD 6.1 we use a board select code in each command sent to the LCB to address the individual modules that make up the firmware suit loaded to the Virtex part. This note pretends to fix the identity of the modules selected by each bit of the board select bit field used in the command structure. There are 10 bits available in this field. Torrent currently supports the use of the lowest order five bits although eight bits can be specified (with minor modification) in the Torrent architecture. The table below identifies the correspondence:

Torrent firmware module addressing
Board Select Bit Module Selected Module Abbreviation Module Identity Code Module purpose
0 (0x01) LCB Control Module LCB 201 Communications and digital control of the Torrent DHE
1 (0x02) Power Supply Services PSM 202 Safety, Control, and telemetry of the power supply board (PSM)
2 (0x04) Configuration Services CFG 203 Configuration data management (eeprom data), LCB clock control and sequencer (CFG)
3 (0x08) Pixel Data Services PIX 204 Pixel data memory and descrambling logic common to OUV and IR (PIX)
4 (0x10) Analog Front End Control (AFE) AFE 205 Analog front end electronics control and pixel acquisition (IR or OUV).
5 (0x20) Spare select bit SPR1 Not assigned Spare module select bit.
6 (0x40) Spare select bit SPR2 Not assigned Spare module select bit.
7 (0x80) Clock Services CLK 208 Clock control module.

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Standard Data Destination Codes for Communication

The LCB_Control module supplies four duplex channels of communications with the DHE. These four comms channels are: Serial FPTP (Systran Emulation), GIGe (Gigabit ethernet), UART (via serial at 9600 Baud, no handshake), and the SYNC port that links to other slave/master DHE's. The comms destination bits set the required destination for these devices. Setting more than one bit results (mostly !) in parallel transmission to all devices.

Comm Device bit assignments
Bit Number Comm Device
0 ("0001") Serial FPDP
1 ("0010") SYNC Port
2 ("0100") UART Port
3 ("1000") GIGe Port

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Standard Register Addresses for Firmware Modules

Each firmware module must supply several registers to support the automatic recognition and configuration processes of the PAN computer. These module addresses are shown below with their functional description:

Standard Torrent Module Registers
Address Register Name Write / Read Register purpose
0xFFFF CodeId 32-bit read only Version number of the firmware module code as an integer. Divide by 100 for major / minor version.
0xFFFF RebootCmd 32-bit Write only (data discarded) Write to this register to warm reboot the LCB. All module select bits must be high i.e. 0xFF.
0xFFFE ModuleId 32-bit read only Module identification number of the firmware module - see section on Firmware Module Addressing and Identity Codes
0xFFFE ResetCmd 32-bit Write only (data discarded) Write to this register to reset the module. Multiple module select bits may be specified in the same command. Writing to this location with the all board select bits set high effects a general LCB system reset to all modules and the wishbone bus infrastructure.
0xFFFD Status 32-bit Read only Read of module status word - Data is module specific.

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Power Supply Status word definition

The power supply monitors the state of the hardware protection circuits on the LCB-MEZ board. These status bits, when true, indicate a hardware protection fault condition that has interrupted the power supply to one or both of the AFE boards. This status regester is (usually) read as an attribute from the DHE at address 0x016F. The attribute name is PwrSupplyStatus.The status bits and their function definitions are shown below :

Power Supply Status Register
Bit Purpose Bit Purpose
7 AFE-1 VANA Power Protection Active 3 AFE-1 / AFE-2 VHV Power Protection Active
6 AFE-1 VCB Power Protection Active 2 Vbb supply active
5 AFE-2 VANA Power Protection Active 1 AFE Power Up Sequence Complete / AFE Power is _ON_
4 AFE-2 VCB Power Protection Active 0 Power Supply Power Up Sequence Complete / Power is Available

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AFE Mezzanine Override register bit definitions

The mezzanine override register allows you to independently control the AFE power enable bits for the mezzanine board. This is _ONLY_ used for testing purposes since indiscriminate enabling power supplies can cause you to exceed the power supply load capabilities. This register is read and write at address 0x202 in the PSM module

Mezzanine Override Register
Bit Purpose Bit Purpose
7 Not used 3 Not used
6 AFE 2 +/- VHV supply enable 2 AFE 1 +/- VHV supply enable
5 AFE 2 +/- VCB supply enable 1 AFE 1 +/- VCB supply enable
4 AFE 2 +/- VANA supply enable 0 AFE 1 +/- VANA supply enable

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DheTempSensorSlct Register Value Significance

This register select which temperature sensor in the DHE is to be used for feedback in the DHE temperature servo loop. The selection of the sensor is based upon a 1 Of 8 (3-bit) code set into the DheTempSensorSlct attribute. The codes are :

DheTempSensorSlct Register Significance
Code Selected Temp Sensor
0 ("000") FPGA temperature sensor (default)
1 ("001") LCB_temperature0
2 ("010") LCB_temperature1
3 ("011") AFE1_temperature0
4 ("100") AFE1_temperature1
5 ("101") AFE2_temperature0
6 ("110") AFE2_temperature1
7 ("111") Load feedback from PAN attribute write (for testing purposes)

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Sequencer State Register Bit Assignments for Firmware Modules

Each firmware module that requires to know the sequencer state information provides a 32-bit register at address 0xFFF0. The sequencer uses this register to periodically write the sequencer state information to all modules that use this address. The lower 16-bits of the register are static values and may be used to indicate the current mode of the sequencer function (e.g. ROI Readout Mode, Digital Averaging Enabled, etc.). The top 16-bits (31:16) are strobe signals that indicate an event during the sequencer operation (Frame Start, Line Start, etc.) and these bits persist for, and are synchronous to one SysClk cycle before being cancelled. The table below indicates the significance of the Sequencer State Register.

Sequencer State Register Assignments
Bit Signal Type Used By Bit Signal Type Used By
31 FrameStartSync Strobe AFE 15 Spare Static n/a
30 LineStartSync Strobe AFE 14 Spare Static n/a
29 Spare Strobe n/a 13 Spare Static n/a
28 Spare Strobe n/a 12 Spare Static n/a
27 Spare Strobe n/a 11 Spare Static n/a
26 Spare Strobe n/a 10 Spare Static n/a
25 Spare Strobe n/a 9 Spare Static n/a
24 Spare Strobe n/a 8 Spare Static n/a
23 Spare Strobe n/a 7 Spare Static n/a
22 Spare Strobe n/a 6 Spare Static n/a
21 Spare Strobe n/a 5 Spare Static n/a
20 Spare Strobe n/a 4 Spare Static n/a
19 Spare Strobe n/a 3 Spare Static n/a
18 Spare Strobe n/a 2 Spare Static n/a
17 Spare Strobe n/a 1 Spare Static n/a
16 Spare Strobe n/a 0 Spare Static n/a

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Addresses for I2C Bus Devices / FPGA Boot Code Version Selection

There are five I2C buses associated with the Torrent DHE; one I2C bus for every physical board (LCB, PSM, TSM, AFE1, AFE2). There are four devices attached to each bus. This table lists their addresses and describes their use. During the DHE initialization (just after boot), the SDA signal line of each I2C bus is used to detect the presence of the physical board. The SCL signal for AFE1 (AFE_SCL_SRC0) is also used to direct the revision of the code that is booted at power up. This signal is pulled 'high' through a 50K Ohm pullup to 3.3v on the LCB. IR AFE boards should pull this signal low via a 3.3K Ohm resistor to the VPIFC GND return. This will select revision zero of the XF32P eeprom (LCB U43) boot code to load to the FPGA for IR operation. CCD AFE boards should leave this signal floating to select revision 1 of the boot code for VIS operation.

I2C Bus Module Addresses
Address Device Type Description
0x48 MCP9803 Temperature sensor used to control the DHE operating temperature and supply telemetry
0x49 MCP9803 Temperature sensor used to control the DHE operating temperature and supply telemetry
0x50 DS28CM00 48-bit silicon serial number as unique identity for each hardware board. Only the ls 32-bits are read.
0x54 24AA128 Calibration coefficient store space. Page written and read; 256 Pages each with 16 x 32-bit words.

For PAN control of these resources there are several registers that are used to read and write to the I2C devices. These are listed in the following table:

Control of I2C EEProm, Temperature sensors, and Silicon Serial Numbers
Attribute name Address Write Value Read Value Description
DetectI2CBus 0x0012 Anything Bit(4)=AFE2 Detected,
Bit(3)=AFE1 Detected,
Bit(2)=TSM Detected,
Bit(1)=PSM Detected,
Bits(0)=always '1'		 5-bit read/write register. Write anything to initiate I2C bus detection, Read to see hardware devices available
ReadI2CBusTemps 0x0013 Bits(20:16)=I2C Channel Addr, Bit(0)=Temperature sensor 1 or 2. Not Accessible 32-bit write register. Write to initiate I2C temperature sensor read cycle and update read only registers.
ReadI2CBusSerial
Numbers		 0x0014 Bits(20:16)=I2C Channel Addr. Not Accessible 32-bit write register. Write to initiate I2C silicon serial number reads and update read only registers
eepRdCmdReg 0x0020 Bits(20:16)=I2C Channel Addr. Bits(7:0)=EEProm page address. Bit(31)=I2C manager busy,
Bit(30)= Error occurred during read - bad I2C acknowledge.		 32-bit read/write register. Command register to select and read an eeprom page
eepWrtCmdReg 0x0021 Bits(20:16)=I2C Channel Addr. Bits(7:0)=EEProm page address. Bit(31)=I2C manager busy,
Bit(30)= Error occurred during write - bad I2C acknowledge.		 32-bit read/write register. Command register to select and write an eeprom page

Channel Address values for the physical hardware boards are: LCB = 1, PSM = 2, TSM = 4, AFE1 = 8, AFE2 = 16.

For the ReadI2CBusTemps, ReadI2CBusSerialNumbers, and eepWrtCmdReg commands, multiple channel addresses are allowed (i.e. you can read multiple temperature sensors or write the same data to multiple EEproms using just one command transaction).

For the eepRdCmdReg command, only one unique channel address is allowed.

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Bit significance for the LED_1_Slct and LED_2_Slct indicator attributes

There are two 8-bit registers assigned to provide visual indication of the internal signals of the FPGA. These registers are read / write. By setting a bit true the indicator (LED1 or LED2) will flash briefly (25ms) every time the selected signal becomes active true. LED1 is currently mounted on the Sync In port connector and LED2 is mounted on the Sync Out Port connector. The tables below indicate the significance of each attribute bit.

LED1 Signal Select Bits
bit signal
7 BusReset
6 SlaveErrOut(4)
5 SlaveErrOut(3)
4 SlaveErrOut(2)
3 SlaveErrOut(1)
2 SlaveErrOut(0)
1 CfgCycleRequest
0 LcbCycRequest
LED2 Signal Select Bits
bit signal
7 SRC_SYNC_OUT
6 SNK_SYNC_IN
5 V33_SYNC_OUT
4 V300_POLARITY
3 V180_PWR_EN_N
2 V80_PWR_EN_N
1 VFAN_PWR_EN_N
0 MCLK_SEL_N

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DbgSigSlct attribute values

This attribute controls the selection of a group of eight signals that are presented on the CFGDATA(7:0) signals (connector J4) on the LCB. By setting the attribute to different values, the hardware debug signals are available for diagnostic use. The attribute accepts values from zero to ten. The list below shows the significance.

DbgSigSlct Attribute values
Value Signal Group
0 Signals off
1 LCB Control Signal group
2 PSM Services Signal group
3 CFG Services Signal group
4 PIX Services Signal group
5 AFE Control Signal group
6 Signals off - Future AFE2 Signal group
7 Signals off - Spare
8 CLK Services Signal group
9 System Bus Signal group
10 Auxiliary Signal group

These tables list the individual signals for each group.

DbgSigSlct = 1 - LCB Control signal assignments
bit signal
7 GIGe_PIXEL_CLK
6 GIGe_FVAL
5 GIGe_LVAL
4 GIGe_DVAL
3 PixDataRdy
2 GIGe_BULK0_CLK
1 GIGe_BULK0_RXD
0 LinkUp
DbgSigSlct = 2 - PSM Services signal assignments
bit signal
7 AfePwrIsOn
6 TEMP_2_SNS
5 TEMP_1_SNS
4 LOGIC_SYNC
3 V300_SYNC
2 V180_SYNC
1 V80_SYNC
0 V33_SYNC
DbgSigSlct = 3 - CFG Services signal assignments
bit signal
7 MstrScl
6 MstrSdain
5 MstrSdaOut(2)
4 MstrWrtEn
3 SYNC_DHE
2 SE_OUT
1 SE_READY
0 SYNC_POWER
DbgSigSlct = 4 - PIX Services signal assignments
bit signal
7 MemInitDone
6 DlyClkLocked
5 app_af_wren
4 app_af_cmd(0)
3 app_af_cmd(1)
2 rd_data_valid
1 app_wdf_wre
0 MemoryDataClk
DbgSigSlct = 5 - AFE Control signal assignments
bit signal
7 DacDevData(17)
6 DacDevData(16)
5 AFE_CLKBIAS(77)
4 AFE_CLKBIAS(48)
3 SerialSync(0)
2 SerialData(0)
1 SerialClk(0)
0 DacCtrlDataRdy
DbgSigSlct = 8 - CLK Services signal assignments
bit signal
7 DCLK_FEED
6 BCLK_FEED
5 CLK_CTRL_CS_N
4 CLK_CTRL_GOE
3 CLK_CTRL_LOCK
2 CLK_CTRL_SYNC
1 CLK_CTRL_DATA
0 CLK_CTRL_CLK
DbgSigSlct = 9 - System signal assignments
bit signal
7 Mstr1Grnt
6 Mstr0Grnt
5 SlaveCycle
4 SlaveWrite
3 SlaveError
2 StatusEnable
1 SlaveAck1
0 SlaveAck0

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Wishbone system status signal assignments for Firmware Modules

Each firmware module can supply eight bits of 'out of band' status information which is used to transport slow signals (such as static configuration values) to other modules. The routing is controlled by the System Intercon module which employs static assignment to route input status bits to the global 32-bit output status sent to the other modules slave interface. The table below shows the routing information for the system at FPGA version level 2.22.

Global Status Assignments
Bit Signal Origin Used By Bit Signal Origin Used By
31 ShutDownQuick PSM AFE 15 n/a n/a Spare
30 AsyncFlag LCB CFG 14 n/a n/a Spare
29 ReadoutInProgress CFG AFE 13 n/a n/a Spare
28 FrameStart CFG AFE 12 n/a n/a Spare
27 LineStart CFG AFE 11 n/a n/a Spare
26 MemPwrEnbld PSM PIX 10 n/a n/a Spare
25 ClocksAreLocked CLK PIX 9 n/a n/a Spare
24 AFEPowerOn PSM AFE 8 StreamMode PIX AFE
23 VHVPolarity PSM AFE 7 DheIsSlave CFG LCB, CLK
22 AFE 2 is enabled AFE PSM 6 Pixels16 PIX LCB
21 AFE 1 is enabled AFE PSM 5 PackedPixels PIX LCB
20 n/a n/a Spare 4 AFE2_Detected CFG PSM, AFE
19 n/a n/a Spare 3 AFE1_Detected CFG PSM, AFE
18 n/a n/a Spare 2 TempChanSlct(2) PSM CFG
17 n/a n/a Spare 1 TempChanSlct(1) PSM CFG
16 n/a n/a Spare 0 TempChanSlct(0) PSM CFG

These next tables show the module status output assignments:

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Local Control Board Module Status Output Assignments

Local Control Board Module (LCB) System Status Output Assignments
Bit Signal Description Bit Signal Description
7 n/a Spare 3 n/a Spare
6 n/a Spare 2 n/a Spare
5 n/a Spare 1 n/a Spare
4 n/a Spare 0 AsyncFlag True after reboot while waiting for a comm port async command
Local Status significance
Bit Signal Description Bit Signal Description
0 AsyncFlag_i Awaiting communication sync command from PAN 7:1 n/a Spares
8 CommDeviceBusy_i The science data comms channel is blocked up 9 SfpdpLossOfSig_i Systran link down. No carrier present signal
10 SfpdpTxFault_i There is a hardware fault in the Systran optical transmitter part 11:12 n/a Spares
28:13 WbErrorStats_i(15:0) Wishbone bus error statistics      

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Power Supply Services Module Status Output Assignments

Power Supply Services Module (PSM) System Status Output (0xFFFD) Assignments
Bit Signal Description Bit Signal Description
7 n/a Spare 3 ShutDownQuick Emergency shutdown signal
6 VHVPolarity True indicates N-Channel mode (positive VHV) 2 TempChanSlct(2) 1 of 8 slct of DHE temperature control sensor
5 AFEPowerOn The AFE boards have VANA+/- powered up 1 TempChanSlct(1) 1 of 8 slct of DHE temperature control sensor
4 MemPwrEnbld 1.8v Memory power is available. 0 TempChanSlct(0) 1 of 8 slct of DHE temperature control sensor
PSM Local Status register (0xFFFC) significance
Bit Signal Description Bit Signal Description
0 VFanTempSensorSlct_reg(0) Same signal as system status 1 VFanTempSensorSlct_reg(1) Same signal as system status
2 VFanTempSensorSlct_reg(2) Same signal as system status 3 ShutDownQuick Panic !!
4 TsmPresent_i Indicates that the TSM is present. 5 n/a Spare
6 n/a Spare 7 n/a Spare
PSM Power Status Register (0x020F) significance
Bit Signal Description Bit Signal Description
0 PrimaryPwrStat Primary power is available 1 AfePwrStat AFE power is available
2 VbbEnableFlag Vbb supply is enabled (after safety conditioning) 3 AfeV300Fail Mezzanine Fail indicator for VHV
4 Afe2V180Fail Mezzanine Fail indicator for VCB on AFE2 5 Afe2V80Fail Mezzanine Fail indicator for VANA on AFE2
6 Afe1V180Fail Mezzanine Fail indicator for VCB on AFE1 7 Afe1V80Fail Mezzanine Fail indicator for VANA on AFE1
PSM Mezzanine Override Register (0x0202) significance
Bit Signal Description Bit Signal Description
7:0 MezOverRide_reg As written by PAN 8 Afe1V80Fail Mezzanine Fail indicator for VANA on AFE1
9 Afe1V180Fail Mezzanine Fail indicator for VCB on AFE1 10 AfeV300Fail Mezzanine Fail indicator for VHV
11 n/a Not used 12 Afe2V80Fail Mezzanine Fail indicator for VANA on AFE2
13 Afe2V180Fail Mezzanine Fail indicator for VCB on AFE2 14 AfeV300Fail Repeat of Mezzanine Fail indicator for VHV

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Configuration Services Module Status Output Assignments

Configuration Services Module (CFG) System Status Output Assignments
Bit Signal Description Bit Signal Description
7 n/a Spare 3 DheIsSlave The DHE is configured as a slave device in a multi-DHE system
6 n/a Spare 2 AFE2_Detected The AFE2 board is physically present
5 LineStart Indicates a new row beginning 1 AFE1_Detected The AFE1 board is physically present
4 FrameStart Indicates a new frame beginning 0 ReadoutInProgress Sequencer is actively reading detector
Local Status significance
Bit Signal Description Bit Signal Description
0 ReadoutActive Sequencer EFR bit to indicate that ... 1 AFE0_ModuleDetect AFE1 has been detected during the I2C bus search
2 AFE1_ModuleDetect AFE2 has been detected during the I2C bus search 3 DheIsSlave DHE is operating as a slave DHE
4 FrameStart A frame start flag has been issued in the pixel stream 5 LineStart A line start flag has been issued in the pixel stream
15:6 not used Spare 19:16 BusTimeoutReg Sequencer Wishbone master Bus Timeout Register
23:20 BusGrantReg Sequencer Wishbone master Bus Grant error register 27:24 BusErrorReg Sequencer Wishbone master Bus slave Error register
31:28 BusEventStatusReg Sequencer Wishbone master Bus status register      

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Pixel Services Module Status Output Assignments

Pixel Services Module (PIX) System Status Output Assignments
Bit Signal Description Bit Signal Description
7 n/a Spare 3 n/a Spare
6 n/a Spare 2 StreamMode Pixel data path configured for Stream Data acquisition mode i.e. no memory buffering
5 n/a Spare 1 Pixels16 Pixel data has been scaled to 16-bits by the PIX module.
4 n/a Spare 0 PackedPixels Each 32-bit pixel data word contains 2 x 16-bit pixels.
Local Status significance
Bit Signal Description Bit Signal Description
0 MemCntrInitDone_i Memory system calibrated and ready for use 31:1 n/a Spares

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Analog Front End Control Module Status Output Assignments

System Status Output Assignments
Bit Signal Description Bit Signal Description
7 n/a Spare 3 n/a Spare
6 n/a Spare 2 n/a Spare
5 n/a Spare 1 afe_enbl_reg(1) True when AFE 2 is enabled via AfeInterfaceEnbl
4 n/a Spare 0 afe_enbl_reg(0) True when AFE 1 is enabled via AfeInterfaceEnbl
Local Status significance
Bit Signal Description Bit Signal Description
0 RfshTpActFlag Test points are being refreshed 1 RfshActiveFlag DAC and Test Points are being refreshed
4 tp_fifo_empty The Test point write FIFO is empty 5 dac_fifo_empty The DAC write FIFO is empty
8 TelScanGo Telemetry scan is active 9 RfshTpWrtFifo transfer test point index to tp write fifo

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Clock Services Module Status Output Assignments

Clock Services Module (CLK) System Status Output Assignments
Bit Signal Description Bit Signal Description
7 n/a Spare 3 n/a Spare
6 n/a Spare 2 n/a Spare
5 n/a Spare 1 n/a Spare
4 n/a Spare 0 ClocksAreLocked Clock Synthesizer has lock and clocks are good
Local Status significance
Bit Signal Description Bit Signal Description
0 LockDetect_i The clock generator is running locked to the reference frequency 31:1 n/a Spares

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Loading Firmware code to the LCB eeprom

Loading the PROM Code

1) Point the Impact tool to the systemBuildFilename.ipf tool by right clicking the "Configure Target Device"/"Properties" menu item.

2) Load Impact and confirm that the boundary scan devices have the correct file associations, systemBuildFilename.mcs and systemBuildFilename.bit.

3) Right click the xcf32p device and select "Programming Properties". Make sure the following boxes are checked:

  • Verify
  • Erase Entire Device
  • Parallel Mode
  • During Configuration: PROM is Slave

All other check boxes should be clear

4) Right click on the xcf32p device, select "Load Configuration Revision", and set to 0.

5) Right click on the xcf32p device, select "Set Erase Properties", and set to Erase Entire Device.

6) Right click on the xcf32p device and select "Program" to program the device. This operation will take a few minutes.

Creating the PROM Programming MCS File

This is the procedure to create the PROM MCS file from the FPGA BIT file.

1) In the "Processes" window of the Xilinx ISE project navagator, click on "Configure Target Device" and then double click "Generate Target PROM/ACE File. This will start the Impact tool and display a Welcome page.

2) Select "Prepare a PROM File" and clock Next.

3) A new page is displayed to prepare the PROM files. Set the following:

  • Target - click "Xilinx PROM" radio button
  • PROM File Format - click "MCS" radio button
  • Checksum Fill Value - set to FF
  • PROM File Name - type in the filename, typically systemBuildName_VerXXX.
  • Location - browse to the directory where the BIT file is located, usually the SystemBuild directory.

Click next.

4) Select the PROM mode page - set the following:

  • I am using a Xilinx PROM in a Parallel Mode.
  • The data bus width for my FPGA is The same as the data width for my PROM device.

Click next.

5) Specify Xilinx PROM Device page - set the following:

  • Set the Enable Revisioning check box.
  • Set the Number of Revisions to 2.
  • Select a PROM in the pulldown menus "xcfp" and "xcf32p [32M]", and click Add. Position 0 and Part Name xcf32p should appear in the field.

Click next.

6) A file generation summary is displayed - click finish.

7) The PROM file formatter is launched and a pop-up to start adding device file to Revision:0 is displayed. Click OK.

8) The files in the project location directory are displayed. Select the appropriate BIT file and click OPEN.

9) Another pop-up appears Would you like to add another design file to Revision 0:? Click NO

10) Another pop-up appears Start adding device file to Revision:1. Click OK.

11) The files in the project location directory are displayed again. Select the same BIT file as in step 8 and click OPEN.

12) Another pop-up appears Would you like to add another design file to Revision 1:? Click NO.

13) Another pop-up appears You have completed the device file entry - click OK.

14) In the "Configuration Operations" tab of the ISE Navigator double-click on the Generate File operation. This will complete the process and a window should pop-up indicating that it succeeded.

Torrent Mechanical

Mechanical Parts
TRNT-EL-02-1001 CARD GUIDE MOUNT [112]
TRNT-EL-02-1002 CONTROLLER BOTTOM PLATE [113]
TRNT-EL-02-1003B CONTROLLER REAR PANEL [114]
TRNT-EL-02-1004A CONTROLLER FRONT PANEL [115]
TRNT-EL-02-1005 CONTROLLER CROSS RAIL RIGHT [116]
TRNT-EL-02-1006 CONTROLLER CROSS RAIL LEFT [117]
TRNT-EL-02-1007B CONTROLLER REAR PANEL INSERT [118]
TRNT-EL-02-1008B CONTROLLER COVER [119]
TRNT-EL-02-1010B PSM ENCLOSURE BASE [120]
TRNT-EL-02-1011 PSM ENCLOSURE BOTTOM COVER [121]
TRNT-EL-02-1012A PSM ENCLOSURE FILL PLATE [122]
TRNT-EL-02-1013 CONTROLLER SUPPORT RAIL SPACER [123]
TRNT-EL-02-1016 CONTROLLER PCB SUPPORT RAIL REAR [124]CON
TRNT-EL-02-1017 CONTROLLER PCB SUPPORT RAIL FRONT [125]
TRNT-EL-02-1019A CONTROLLER EMI PLATE [126]
TRNT-EL-02-1020 DHE MOUNTING TAB [127]
TRNT-EL-02-1021B TRANSITION MODULE BASE PLATE [128]
TRNT-EL-02-1022B TRANSITION MODULE ISOLATION CONNECTOR PLATE [129]
TRNT-EL-02-1023C TRANSITION MODULE ISOLATION RAIL [130]
TRNT-EL-02-1024A TRANSITION MODULE BASE HEADER [131]
TRNT-EL-02-1025B TRANSITION MODULE SIDE PLATE, LEFT [132]
TRNT-EL-02-1026B TRANSITION MODULE SIDE PLATE, RIGHT [133]
TRNT-EL-02-1027A TRANSITION MODULE UTILITY BOARD HEADER [134]
TRNT-EL-02-1028B TRANSITION MODULE BASE TOP COVER PLATE TAB [135]
TRNT-EL-02-1029A TRANSITION MODULE BASE FRONT COVER [136]
TRNT-EL-02-1030A TRANSITION MODULE BASE TOP COVER [137]
TRNT-EL-02-1031 ETHERNET BOARD STANDOFF [138]
TRNT-EL-02-1032 ETHERNET BOARD COVER [139]
TRNT-EL-02-1034B Hex Jam Nut .688-24 [140]
TRNT-EL-02-1035B Hex Jam Nut 1.063-18 [141]
TRNT-EL-02-1036A Hex Jam Nut 1.188-18 [142]
TRNT-EL-02-1037A FINNED BLWR HSG [143]
TRNT-EL-02-1038 HSG CVR [144]

Torrent Construction

These documents outline assembly procedures for constructing the Torrent DHE. They are specifically applicable to techniques used at NOIRLabs but presented here as a help to understanding the assembly process associated with the various mechanical and electrical modules.

Parts Kit Documents
TRNT-EL-02-0000 Blank Dewar Interface kit [145] Rev -0D-
TRNT-EL-02-0014 Transition Module Base Kit [146] Rev -0D-
TRNT-EL-02-0015 KPNO Dewar Connector Plate Kit [147] Rev -0D-
TRNT-EL-02-0016 CCD Flex Cable Kit [148] Rev -0D-
TRNT-EL-02-0017 LCB Kit [149] Rev -0D-
TRNT-EL-02-0018 Controller Base Kit [150] Rev -0D-
TRNT-EL-02-0020 External Connector Kit [151] Rev -0D-
TRNT-EL-02-0021 TSM Covers Kit [152] Rev -0D-
TRNT-EL-02-0022 Controller Cover Kit [153] Rev -0D-

Assembly Documents
TRNT-EL-02-0001A DETECTOR HEAD ELECTRONICS [154]
TRNT-EL-02-0002B CONTROLLER ASSEMBLY [155]
TRNT-EL-02-0003C TRANSITION MODULE ASSEMBLY [156]
TRNT-EL-02-0004B POWER SUPPLY MODULE [157]
TRNT-EL-02-0005A CCD PREAMP TRANSITION BOARD [158]
TRNT-EL-02-0006B TRANSITION MODULE CHASSIS [159]
TRNT-EL-02-0007B BLOWER HOUSING [160]
TRNT-EL-02-0008A CONTROLLER MODULE CHASSIS [161]
TRNT-EL-02-0009 CONTROLLER MODULE PCB MOUNT REAR [162]
TRNT-EL-02-0010 CONTROLLER MODULE PCB MOUNT FRONT [163]
TRNT-EL-02-0011A ETHERNET BOARD ASSEMBLY [164]
TRNT-EL-02-0012B LCB ASSEMBLY [165]
TRNT-EL-02-0024 Torrent Assembly Steps - Controller Module [166] Rev -A-
TRNT-EL-02-0025 TRAN ISOL PLT [167]
TRNT-EL-02-0026 AFE EXT BRD ASSY [168]
 

Torrent Test and Calibration Procedures

TRNT-TS-01-0002 Board Test Requirements [169] Rev 2

Torrent Engineering Change Orders (ECO)

ECOFORM TEMPLATE [170]
Master ECO List [171]
TRNT-001 [172]
TRNT-002 [173]
TRNT-003 [174]
TRNT-004 [175]
TRNT-005 [176]
TRNT-006 [177]
TRNT-007 [178]
TRNT-008 [179]
TRNT-009 [180]
TRNT-010 [181]
TRNT-011 [182]
TRNT-012 [183]
TRNT-013 [184]
TRNT-014 [185]
TRNT-015 [186]
TRNT-016 [187]
TRNT-017 [188]
TRNT-018 [189]
TRNT-019 [190]
TRNT-020 [191]
TRNT-021 [192]
TRNT-022 [193]
TRNT-024 [194]
TRNT-025 [195]
TRNT-026 [196]
TRNT-027 [197]
TRNT-028 [198]
TRNT-029 [199]
TRNT-030 [200]
TRNT-031 [201]
TRNT-033 [202]
TRNT-034 [203]
TRNT-035 [204]
TRNT-036 [205]
TRNT-037 [206]
TRNT-038 [207]
TRNT-039 [208]
TRNT-040 [209]
TRNT-041 [210]

 

Torrent System Configuration Data

These system configuration data packages can be used as templates for future instrument configuration sets. They are offered 'as is' without any warranty as to their operational state or suitability of purpose to other implementations.

Configuration _basicCCD [211] - Test configuration for the Borg tool
Configuration _bill [212] - Laboratory system which always works
Configuration _chile1 [213] - Used to characterize and test the prototype Torrent DHE against the requirements document
Configuration _chiron [214] - Operational configuration running an E2V 4k x 4k detector on the Chiron spectrograph

Source URL (modified on 08/02/2012 - 10:19): http://www.ctio.noao.edu/noao/content/Torrent-Technical-Documents

Links
[1] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT_DataSheet_Rev%2041.pdf
[2] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT-AD-11-0001_Torrent_DHE_Architecture_Rev_5.0.pdf
[3] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT-AD-11-0001_Torrent_Performance_Requirements_Rev_0.0.pdf
[4] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT-AD-04-0001_Torrent_DHE_Compliance_Tests_Rev_2.5.pdf
[5] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT-AD-04-0002_Report_on_the_DHE_Compliance_Tests_Rev_1.0.pdf
[6] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/TRNT-AD-01-0001_rOD.pdf
[7] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/TRNT-AD-01-0003_ICD_7.3_Torrent_DHE_LCB_to_AFE_Interface_Description_Rev_0.pdf
[8] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/TRNT-AD-01-0004_ICD_7.4_Torrent_DHE_PSM_to_LCB_Interface_Description_Rev_0.pdf
[9] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/TRNT-AD-01-0006_ICD_7.6_Torrent_DHE_PSM_to_TSM_Interface_Description_Rev_0.pdf
[10] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Torrent_User_Survey_Rev4.pdf
[11] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT-AD-10-0001.xls
[12] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TRNT-EL-05-0001_System_Interconnect_Rev_0D.pdf
[13] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT-EL-01-0001_Controller_Grounding_Scheme_Rev_A.pdf
[14] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TRNT-AD-08-0007%20DHE%20Hardware%20Description%20R1.1.pdf
[15] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Licensing/Monsoon_License_Rev_1.0.pdf
[16] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-EL-04-0002_rB_Asbly.pdf
[17] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-EL-04-1002_rB_Fab.pdf
[18] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-EL-04-2002_rB_Sch.pdf
[19] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/NOAO_TRNT_3002.zip
[20] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-EL-04-4002_rB_PrtLst.pdf
[21] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/torrentfpga_ver222.bit
[22] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TorrentFpga_Ver222.mcs
[23] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-TS-01-0003_LCB_Test_Procedure_rev_0.pdf
[24] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-0003_rA3_asbly.pdf
[25] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-1003_rA.pdf
[26] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-2003_rA4_Sch.pdf
[27] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-3003_rA_layout.pdf
[28] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-4003_rA5_PrtLst.pdf
[29] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-0001_rB_PSB_Asbly.pdf
[30] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-1001_rB_PSB_FabDetail.pdf
[31] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-2001_rB_PSB_Sch.pdf
[32] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-3001_PSB.zip
[33] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-4001_rB_PrtLst.pdf
[34] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-0004_rC_AFE_AsblyDwgl.pdf
[35] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-1004_rC_AFE_FabDetail.pdf
[36] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-2004_rC1_AFE_Sch.pdf
[37] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-3004_rC_AFE_Artwk.pdf
[38] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-4004_rC1_PrtLst.pdf
[39] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/AFE_Calibration_Worksheets.xls
[40] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-0008_rOD.pdf
[41] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-1008_rOD.pdf
[42] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-2008_rOD_Sch.pdf
[43] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-3008_rOD.pdf
[44] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-TS-01-0004_AFE-CCD_Test_Procedure_Rev_0.pdf
[45] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-0007_rC1_asby.pdf
[46] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-1007_rC_fab.pdf
[47] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-2007_rC1_Sch.pdf
[48] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-4007_rC1.xls
[49] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-0007_rB_Asby.pdf
[50] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-1007_rB_FabDetl.pdf
[51] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-2007_rB1_Sch.pdf
[52] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-3007_rB_artwork.pdf
[53] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-4007_rB2_PrtLst.pdf
[54] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-0009_rA1_Asbly.pdf
[55] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-1009_rA_fab.pdf
[56] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-2009_rA2_SCH.pdf
[57] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-3009_rA.pdf
[58] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/NOAO-TRNT-1009.zip
[59] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-4009_rA4_PrtLst.pdf
[60] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-TS-01-0005_TSM-UTIL_Test_Procedure_Rev_0.pdf
[61] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-0005_rA_Asbly.PDF
[62] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-1005_rA_Fab.PDF
[63] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-2005_rA_Sch.PDF
[64] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/NOAO-TRNT-1005_rA.zip
[65] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-0006_rA_Asbly.pdf
[66] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-1006_rA_Fab.pdf
[67] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-2006_rA_Sch.pdf
[68] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-3006_rA_Artwk.pdf
[69] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0001_CablePSM-util.pdf
[70] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0002_CableShutter_Preflash.pdf
[71] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0003_Ethernet_Shld_wire.pdf
[72] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0006_TSM%20Chassis%20GND%20Wire.pdf
[73] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/MNSN-AD-08-0005_MONSOON_Software_Setup_Rev_2.1.pdf
[74] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0001%20Software%20System%20Description%20Rev%200.pdf
[75] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0002%20borg%20R0.pdf
[76] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0006%20Software%20User%20Manual%20R0.pdf
[77] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0003%20Assimilate%20Rev1.2.pdf
[78] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0004_Torrent_Collector_Rev_1.1.pdf
[79] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0012%20Torrent%20Sequencer%20Description%20R0.pdf
[80] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT_Assembler_Ver_6.zip
[81] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Combined_Attribute_declarations_ver2.22_Rev2.pdf
[82] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/TRNT-AD-08-0011%20AFE%20Control%20Module%20Firmware%20R0.pdf
[83] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Torrent%20LCB%20Firmware%20Design%20Rev%20C3.pdf
[84] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/WishBone%20Bus%20Specification%20From%20OpenCores%20wbspec_b3-1.pdf
[85] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Clock%20Generation%20WorkBookV4%20.xls
[86] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/AFE%20Serial%20device%20control%20list.xls
[87] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PowerSupplySyncAnalysis.xls
[88] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/TorrentFpga_Ver222.zip
[89] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/AFE_Control_Ver221.zip
[90] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CFG_Services_Ver220.zip
[91] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CLK_Services_Ver221.zip
[92] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/DummyModule_V220.zip
[93] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/LCB_Control_Ver222.zip
[94] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PIX_Services_Ver221.zip
[95] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PSM_Services_Ver221.zip
[96] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CmdDecodeFifo.zip
[97] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CommsDemuxPixBuffr_V106.zip
[98] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/I2C_InterfaceV100.zip
[99] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/I2C_Interface_V210.zip
[100] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PixDataMuxFifo_V103.zip
[101] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SeqPatMemCore.zip
[102] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SeqProgMemCore.zip
[103] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SerialFPDP_fifo_5v5.zip
[104] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SyncPortFifo_V100.zip
[105] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Uart_8.zip
[106] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/UartFifo.zip
[107] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/VideoFifo.zip
[108] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Intercon_Ver222.zip
[109] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/WishBoneMasterInterfaceV106.zip
[110] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/WishBoneSlaveInterface_Ver207.zip
[111] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/NOAO_tblock.zip
[112] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1001%20CARD%20GUIDE%20MOUNT.pdf
[113] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1002%20CONTROLLER%20BOTTOM%20PLATE.pdf
[114] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1003B%20CONTROLLER%20REAR%20PANEL.pdf
[115] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1004A%20CONTROLLER%20FRONT%20PANEL.pdf
[116] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1005%20CONTROLLER%20CROSS%20RAIL%20RIGHT.pdf
[117] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1006%20CONTROLLER%20CROSS%20RAIL%20LEFT.pdf
[118] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1007B%20CONTROLLER%20REAR%20PANEL%20INSERT.PDF
[119] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1008B%20CONTROLLER%20COVER.pdf
[120] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1010B%20PSM%20ENCLOSURE%20BASE.PDF
[121] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1011%20PSM%20ENCLOSURE%20BOTTOM%20COVER.pdf
[122] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1012A%20PSM%20ENCLOSURE%20FILL%20PLATE.pdf
[123] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1013%20CONTROLLER%20SUPPORT%20RAIL%20SPACER.pdf
[124] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1016%20CONTROLLER%20PCB%20SUPPORT%20RAIL%20REAR.PDF
[125] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1017%20CONTROLLER%20PCB%20SUPPORT%20RAIL%20FRONT.PDF
[126] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1019A%20CONTROLLER%20EMI%20PLATE.pdf
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[135] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1028B%20TRANSITION%20MODULE%20BASE%20TOP%20COVER%20PLATE%20TAB.pdf
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[143] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1037A_FINNED%20_BLWR_HSG.pdf
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[145] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Manufacturing/TRNT-EL-02-0000%20Blank%20Dewar%20Interface%20kit%20Rev%20-0D-.pdf
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[179] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-008.pdf
[180] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-009.pdf
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[183] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-012.pdf
[184] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-013.pdf
[185] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-014.pdf
[186] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-015.pdf
[187] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-016.pdf
[188] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-017.pdf
[189] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-018.pdf
[190] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-019.pdf
[191] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-020.pdf
[192] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-021.pdf
[193] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-022.pdf
[194] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-024.pdf
[195] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-025.pdf
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[197] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-027.pdf
[198] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-028.pdf
[199] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-029.pdf
[200] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-030.pdf
[201] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-031.pdf
[202] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-033.pdf
[203] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-034.pdf
[204] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-035.pdf
[205] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-036.pdf
[206] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-037.pdf
[207] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-038.pdf
[208] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-039.pdf
[209] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-40.pdf
[210] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/EngineeringChangeOrders/TRNT-41.pdf
[211] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/SystemConfig/_basicCCD.zip
[212] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/SystemConfig/_bill.zip
[213] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/SystemConfig/_chile1.zip
[214] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/SystemConfig/_chiron.zip