MONSOON is an NOIRLab "full open-source" development effort to address the need for detector-limited image acquisition for the next generation of astronomical instruments not only for NOIRLab but for the entire astronomical community.
MONSOON is an architecture for a flexible solution for the acquisition of pixel data from scientific CDD and IR detectors. The architecture provides a front end interfaces to the observing and instrument control software and a back end interface to the observatory data handling system. These interfaces are based the standard "Observatory System Reference Model" which is shown here.
The architecture provides for an extensible and flexible modular structure to cover detector controller applications ranging from a focal plane with a single detector to very large focal planes made from arrays of detectors. The basic hierarchy of a MONSOON Image Acquisition System is shown here.
There are currently three physical implementations of the MONSOON Image Acquisition System Architecture.
MONSOON Orange.
Designed and built to accommodate the requirements for both IR and CCD large focal planes that NOIRLab developed for instrumentation efforts in the early part of the twenty first century. These instrument projects were NEWFIRM, ODI, and LSST.
MONSOON DECam.
Which is the result of the technology transfer to Fermilab - based on the open source nature of MONSOON - to satisfy the requirements for the Dark Energy Camera. This is a variant of the MONSOON Orange design that increases the physical video and clock channel density to suit the prime focus instrument. This design also updates the technology used to implement the hardware.
MONSOON Torrent.
Is a design based on the requirement to normalize the detector controller technology for the NOIRLab System Observatories and supports the small and medium sized focal planes. This design replaces obsolete technology and provides a complete and integrated controller solution for an economic price.
New project initiatives at NOIRLab such as ORION, NEWFIRM, QUOTA, and ODI have defined the need for scalable, multichannel, high-speed image acquisition. Systems of this scale and performance raise new challenges in terms of communication bandwidth, data storage and data processing requirements which are not adequately met be currently existing astronomical controllers. In order to meet this demand, new techniques for not only a new detector controller but rather a new image acquisition architecture, have been defined. These very same concepts can and should be extended to even larger systems. These extremely large scale imaging systems also raise less obvious concerns in previously neglected areas of controller design such as physical size and form factor issues, power dissipation and cooling near the telescope, system assembly/test/ integration time, reliability, and total cost of ownership.
At NOIRLab we have taken efforts to look outside of the astronomical community for solutions found in other disciplines to similar classes of problems. A large number of the challenges raised by these system needs are already successfully being faced in other areas such as telecommunications, instrumentation, aerospace, and others. Efforts have also been made to use true commercial off the shelf (COTS) system elements, and find truly technology independent solutions for a number of system design issues whenever possible.
Any new detector acquisition system should:
This forward looking approach has moved our efforts at NOIRLab toward developing a modular, scalable architecture, which addresses the larger data pipeline and information flow issues, not simply device interface. In reference to the torrential summer rains of Tucson, and the flood of pixels defined by the next generation imaging systems, this system is named MONSOON. MONSOON is more than a controller, but rather an image acquisition system architecture. MONSOON has been specifically designed to meet and exceed the requirements of ORION, NEWFIRM, QUOTA, and ODI.
For information concerning MONSOON Technology please contact: Peter Moore, lead engineer, pmoore_at_noao_dot_edu, +56 51 220 5233 or +56 51 220 5208
MONSOON is a architecture that allows scalable detector controllers to be built. There are three versions of the MONSOON architecture currently in use:
The original version, called MONSOON Orange, is used on a variety of CCD and near infrared detector equipped instruments at the NOIRLab observatories. This version is expandable to meet the requirements of very large focal planes using arrays of detectors. An Orange controller is built using a standard PCI bus card cage and backplane and then populating the bus from selected MONSOON Orange modules to achieve the requirements of the instrument detector. Multiple card cages can be synchronized to an external clock source and the electrical interface to the detector customized using backplane 'Transition' cards. This link provides a data sheet [1] with the technical specifications of the Orange Controller.
The second version of the controller technology was developed completely in house by Fermilab to support the Dark Energy Camera project. This controller is based on the Orange variant and adapted by Fermilab to provide more channel density to accommodate the requirements of supporting seventy seven detectors in the focal plane. The CCD detector technology used in the DECam focal plane is P-Channel deep depletion devices from LBNL.
The third version of the controller, called MONSOON Torrent, is a compact eight video channel CCD detector controller designed for smaller focal planes which offers a complete solution to controlling CCD detectors, including detector temperature control and detector back side bias power. This link provides a data sheet [2] with the technical specifications of the Torrent Controller.
This link provides an overall view of applications [3] to which the MONSOON image acquisition system is being used.
This link gives a basic introduction [4] to the technology of MONSOON systems
The MONSOON Generic Pixel Server Software Design [5]
The MONSOON Implementation of the Generic Pixel Server [6]
The Generic Pixel Server Dictionary [7]
Automated Software Configuration in the MONSOON System [8]
Orthogonal Transfer Array Control Solutions Using the MONSOON Image Acquisition System [9]
Dec 2003 - Orange Project Status Review NEWFIRM [10]
Dec 2003 - Orange Project Status Review CTIO [11]
Dec 2003 - Orange Project Status Review SOFTWARE [12]
Dec 2003 - Orange Project Status Review IR SYSTEMS [13]
Dec 2003 - Orange Project Status Review UVIS SYSTEMS [14]
Dec 2006 - Observatory Council PRESENTATION [15]
Aug 2010 - Torrent Project Status Review INTRODUCTION [16]
Aug 2010 - Torrent Project Status Review ELECTRONICS 1 [17]
Aug 2010 - Torrent Project Status Review ELECTRONICS 2 [18]
Aug 2010 - Torrent Project Status Review SOFTWARE [19]
Aug 2010 - Torrent Project Status Review MECHANICAL [20]
Aug 2010 - Torrent Project Status Review MANUFACTURE [21]
Aug 2010 - Torrent for KOSMOS PRESENTATION [22]
Enabling MONSOON technology as an Open Source development has been a principle objective from the concept stages of the project. The choice of technology and methods has always focused on providing controllers that are not hindered by propriety technology and free of licensing and/or royalty fees. The objective to release all technology associated with the MONSOON Image Acquisition System has been fully met.
Open source technology provides many advantages to the user. Some of these advantages are outlined here [23] in this white paper that was presented to NOIRLab management to argue the case for open source development.
The announcement of the release of MONSOON technology to the community by NOIRLab in 2004 is found here [24].
And finally, the open source license agreement for using MONSOON technology is here [25].
Essentially you, as a prospective user of a MONSOON system, are allowed to do anything you like with the technology as long as you do not try to license it as your own property i.e. the open license must be propagated to all future developments using this technology.
You can peruse the documentation, adopt some or all of the technology, modify it it to suit your specific purposes, build it in quantity, sell it, even burn it if you wish; but please do not try to inhibit others from using the technology by licensing it to yourself.
At NOIRLab we are committed to honoring our side of the license agreement. That is, we are committed to disclose all information concerning the MONSOON technology. Most of the information can be found on this web site. However, source files for the circuit board schematics and layouts are relatively large to handle through the hyperlink protocols. If you require the sources or other information that is not directly available on this website please contact Peter Moore - pmoore_at_noao_dot_edu or +56 51 205233 / +56 51 205208.
Open source technology licensing provides many advantages to the user. NOIRLab makes MONSOON Technology available through such a license agreement. Please be aware that while you are welcome to browse the technical material in this area, NOIRLab requires you to agree to the terms and conditions of the license before you begin building things based on the MONSOON designs. This requires you to sign the open source license agreement [25] and return this document to
National Optical-Infrared Astronomy Research Laboratory,
Attention Dr. David Sprayberry,
950 N. Cherry Ave,
Tucson, Arizona, 85719, USA.
Once you have agreed to the terms of use by returning a signed license agreement to NOIRLab we can supply you with the source documentation for the information you require.
The documents that describe the MONSOON technology have a structure based on a document numbering system. The numbering system is identical between the Orange and Torrent versions of the technology. The only difference is that the prefix is changed.
MONSOON Orange document numbers start with a MNSN prefix. The Orange document structure graphic is here [26].
MONSOON Torrent document numbers start with a TRNT prefix. The Torrent document structure graphic is here [27].
These documents control the function and state of inputs to and outputs from the modules that make up a MONSOON Image Acquisition System. There are four main module interfaces that are required to build a MONSOON system. These are:
The PAN is often generically called the data acquisition computer. This interface is governed by MONSOON Interface Control Document level 6. These interfaces are common to the Orange and Torrent systems.
ICD 6.0 MNSN-AD-01-0004 Generic DHE Interface Description [28] Rev 1.0
ICD 6.1 MNSN-AD-01-0005 DHE Interface Description [29] Rev 1.1
This is the control and command interface for the image acquisition system. Levels 4 and 5 of the MONSOON Interface Control Documents define this interaction. These interfaces are common to the Orange and Torrent systems.
ICD 4.0 MNSN-AD-01-0004 Generic Pixel Service Communications Command Response and Data Stream Interface Description [30] Rev 1.1
ICD 5.0 MNSN-AD-01-0003 PAN Communications Command Response and Data Stream Interface Description [31] Rev 1.0
ICD 5.1 MNSN-AD-01-0007 PAN Run-time Configuration Setup and Operating Mode Definition Interface Description [32] Rev 1.0
The interface allows the transport of the pixel data and meta data from the acquisition computer (PAN) to an observatory data handling facility. ICD level 1 governs this interaction (which can be as simple as FITs file generation). These interfaces are common to the Orange and Torrent systems.
ICD 1.0 MNSN-AD-01-0001 Data Handling System [33] Rev 1.0
ICD 1.1 MNSN-AD-01-0012 Data Handling System Interface Status and Data Stream Description [34] Rev 1.0
The manufacturing documents and files available on this site may not reflect the latest optimal configuration of the hardware modules. The documents on this site reflect the configuration of the last production run of the hardware and may not reflect work that was carried out post-production through engineering change orders.
At this point the three versions of the MONSOON Technology (Orange, DECam and Torrent) diverge in the way the hardware is used to implement the functionality. The following links will take you to the details of the hardware, software, and mechanical details of each implementation.
The information contained in this archive are copies of the documentation data base that resides off-site.
The principal purpose of this local archive is to provide information valuable to CTIO personel for the maintenance and testing of the DECAM instrument detector controller system - MONSOON.
All documents carry their original Doc DB number and version so that they may be traced back to the original source.
Every effort is made to maintain the local copies up to date with the latest revisions however, I am not infallible (you may have guessed that). If you find a discrepancy between the documentation and reality please contact Peter Moore (pmoore_at_noao_dot_edu) so that a correction or update can be made.
6563-v1 Front End Electronics - Overview of fault reporting conditions [35]
5749-v2 Test station startup - To start PanView for module testing [36]
(Note that you need a clk board in crate slot 3 and/or a 12Ch Acq board in slot 6)
Terri Shaws' DECam information page - Excellent source of information [37]
DECam System - Electronic Log [38]
DECam System - Telemetry viewer [39]
DECam System - Alarms Browser [40]
DECam System - SISPI web page [41]
355-v22 12 Channel Acquisition Board - How to program [42]
355-v22 12 Channel Acquisition Board - Firmware version history [43]
2299-v11 Clock and Bias Board - Firmware version history [44]
355-v22 12 Channel Acquisition Board - 2010_11_18_acq12_fw_408 [45]
2299-v11 Clock and Bias Board - CBv4.01 [46]
2878-v1 Master Control Board - mcbFull_V1.02 [47]
4080-v7 Master Control Board - MCB_HW1.2FW5.21 [48]
355-v22 12 Channel Acquisition Board - EEPROM image - ccdacq.mcs [49]
2299-v11 Clock and Bias Board - EEPROM image - CBv4.01.mcs [50]
2878-v1 Master Control Board - EEPROM Image - mcb_v1.02.mcs [51]
4080-v7 Master Control Board - EEPROM Image - MCB_v521.mcs [52]
4080-v7 Master Control Board - FPGA Image - MCB_v521.bit [53]
Electronics
5767-v2 Crates - Procedure - Installing or removing connections to front end crates [54]
4654-v2 Crates - Procedure - Type 1 crate disassembly directions [55]
4654-v2 Crates - Procedure - Type 2 and Heater crate disassembly directions [56]
6281-v1 Crates - Procedure - Installing or removing main boards to-from the crate [57]
6281-v1 Crates - Procedure - Installing or removing transition boards to-from the crate [58]
1781-v1 Crates - MS-Word Template - Circuit Board Repair Form [59]
Focal Plane
768-v37 Focal Plane - CCD to Crate and board mapping via VIB - VIB Technical Report [60]
Detectors
5998-v1 Focal Plane - CCD colours [61]
5998-v1 Focal Plane - CCD Name cross references [62]
5998-v1 Focal Plane - Focal plane CCD mapping [63]
5998-v1 Focal Plane - Focal plane CCD Serial numbers [64]
Gerber plot file viewers
Free online viewer - www.gerber-viewer.com [65]
Free download (after registration) - www.mccad.com/FREE_GerberViewer.html [66]
354-v14 12 Channel Acquisition Board - Users Manual [67]
354-v14 12 Channel Acquisition Board - Register map [68]
3150-v9 12 Channel Acquisition Board - Schematics (with ECOs) [69]
3150-v9 12 Channel Acquisition Board - Gerber Plots [70]
3150-v9 12 Channel Acquisition Board - Bill Of Materials [71]
355-v22 3480-v7 12 Channel Acquisition Board - EEPROM Loader Image - ccdacq.mcs [49]
3480-v7 12 Channel Acquisition Transition Board - Schematics (with ECOs) [72]
3480-v7 12 Channel Acquisition Transition Board - Gerber Plots [73]
3480-v7 12 Channel Acquisition Transition Board - Bill Of Materials [74]
1457-v2 12 Channel Acquisition Board - Test Procedures [75]
1458-v1 12 Channel Acquisition Board - Board Test acceptance Criteria [76]
1992-v1 12 Channel Acquisition Board - testing methods presentation August 2008 [77]
4316-v2 12 Channel Acquisition Board - Production test results [78]
4317-v1 12 Channel Acquisition Transistion Board - Production test results [79]
3150-v9 12 Channel Acquisition Board - Changes [80]
2836-v2 12 Channel Acquisition Transition Board - Changes [81]
4345-v3 12 Channel Acquisition Board - ECO 1 - ADC DNL fix [82]
4346-v1 12 Channel Acquisition Board - ECO 2 - Power on bias enable fix [83]
4350-v1 12 Channel Acquisition Board - ECO 3 - VSub spike inhibit [84]
4940-v1 12 Channel Acquisition Board - ECO 4 - DAC range restriction [85]
Each 12-Channel ACQ Transition Board has three cables which run between it and the VIB. The 16 pin cable carries the RTD signals, the 24 pin cable carries the video signals and CCD substrate voltage, and the 32 pin cable carries the bias voltages. For pinout information, see the 12-Channel Transition Module schematics (DOCdb 3480). For system connection map, see the VIB manual (DOCdb 768)
The Samtec part #s of the three cable types are:
EEDP-016-14.80-DS1-RS2-1
EEDP-024-14.80-DS1-RS2-1
EEDP-032-14.80-DS1-RS2-1
length is subject to change!!!
Connectors used on Transition Modules:
MEC8-125-02-L-D-RA1
MEC8-137-02-L-D-RA1
MEC8-149-02-L-D-RA1
Connectors used on VIB:
HSEC8-125-01-S-DV-A
HSEC8-137-01-S-DV-A
HSEC8-149-01-S-DV-A
912-v3 12 Channel Acquisition Board - Samtec cables [86]
912-v3 12 Channel Acquisition Board - Transition module connector [87]
912-v3 12 Channel Acquisition Board - VIB module connector [88]
912-v3 12 Channel Acquisition Board - Samtec cable part numbers [89]
Each Clock Transition Board has two cables which run between it and the VIB. The 60 and 80 pin cables carry the clock signals between the Clcok Transition ond the VIB connectionds to the CCDs. For pinout information, see the Clock Transition Module schematics (DOCdb 2907). For system connection map, see the VIB manual (DOCdb 768)
Samtec Part #s for the two types of Clock Board Cables
HQDP-060-15.00-TTR-TED-1-B
HQDP-080-15.00-TTR-TED-1-B
Samtec Part numbers of Clock Transition
QSH-060-01-L-D-DP-A
QSH-080-01-L-D-DP-A
Samtec Part numbers of VIB Connectors
QSH-060-01-L-D-DP-A
QSH-080-01-L-D-DP-A
916-v7 Clock and Bias Board - Samtec cable [90]
916-v7 Clock and Bias Board - Connectors [91]
916-v7 Clock and Bias Board - Samtec cable part numbers [92]
4208-v1 Kapton cable - Schematic [93]
4210-v1 Kapton cable - Gerbers [94]
4209-v1 Kapton cable - Bill Of Materials [95]
1215-v3 Clock Board - Users Manual [96]
2896-v8 Clock Board - Schematic (with ECOs) [97]
2896-v8 Clock Board - Gerber plots [98]
2896-v8 Clock Board - Bill Of Material [99]
2420-v3 Clock Board - EEPROM Image file - CBv4.01.mcs [50]
Clock Transition Board
2907-v5 Clock Transition Board - Schematics (with ECOs) [100]
2907-v5 Clock Transition Board - Gerber plots [101]
Clock Guider Transition Board
This is a special module constructed to fix a routing error on the VIB East. Clock groups A, B and C must drive G1S, G1S and G1N respectively. If a standard DECam Clock transition card is used with the Clock boards in the Guider backplane, clock group A drives G1S, G2S and G1N. This does not allow the algorithm flexibility required to drive the guiding system. Therefore, a special Clock Guider Transition module was designed.
6183-v2 Clock Guider Transition Board - Schematic [102]
6183-v2 Clock Guider Transition Board - Gerber plots [103]
6183-v2 Clock Guider Transition Board - Bill Of Material [104]
5359-v1 Clock Board - Clock board testing and preliminary acceptance criteria [105]
5359-v1 Clock Board - Test procedure [106]
5358-v1 Clock Board - Production test results [107]
2896-v8 Clock Board - ECOs [108]
2907-v5 Clock Transition Board - ECOs [109]
The Internal Crate Controller board (ICC) monitors the DES crate environment attributes including voltage, temperature, humidity, Vicor power supply cooling fan rotation detection, and crate cooling fan rotation detection. The ICC board will turn off the Vicor power supply, and notify the Instrument Control System, if any monitored attribute goes into a fault condition. The Instrument Control System can also interrogate the ICC to determine the cause of failure as well as force the ICC board to turn off the Vicor power supply.
1527-v70 ICS Interface Host - Quick Start Guide [110]
1527-v70 ICS Interface Host - Users manual [111]
1527-v70 ICC - Firmware Description [112]
1527-v70 ICC - Register Mapping [113]
1527-v70 Fan RPM Board - Design Information [114]
1527-v70 Vicor - DAQ Crate power sequencing [115]
1527-v70 Vicor - Heater Crate power sequencing [116]
1527-v70 - Crate Controller - Bill Of materials [117]
1527-v70 ICC Board - Schematic [118]
1527-v70 ICC Board - Gerber plots [119]
1527-v70 ICC Board - Layers [120]
4264-v1 ICC Board - Power Supply Overvoltage detection circuit modification [121]
1527-v70 Fan Load Board - Schematic [122]
1527-v70 Fan Load Board - Gerber plots [123]
1527-v70 Fan Load Board - Layers [124]
1527-v70 Fan RPM Board - Schematic [125]
1527-v70 Fan RPM Board - Gerber plots [126]
1527-v70 Fan RPM Board - Layers [127]
1527-v70 ICC - Board Checkout [128]
2328-v33 Production Crate - Schematic and description [129]
2328-v33 Production Crate - Bill Of Materials [130]
2328-v33 Production Crate - ICC Board Connector pinouts [131]
2328-v33 Production Crate - ICC Cable & Connector Bill Of Materials [132]
2328-v33 Production Crate - Cooling Fan Plenum Connector pinouts [133]
2328-v33 Production Crate - Power Supply Module Connector pinouts [134]
5740-v1 Production Crate - AC Power cable specification [135]
5739-v1 Production Crate - Crate grounding braid description [136]
1154-v9 Production Crate - Analog backplane connectors [137]
6026-v1 - Heater Controller - Users Manual [138]
6026-v1 - Heater Controller - Production version description [139]
6026-v1 - Heater Controller - Heater driver board schematic [140]
6026-v1 - Heater Controller - Heater driver transition board schematic [141]
6026-v1 - Heater Controller - Heater patch panel board schematic [142]
6026-v1 - Heater Controller - Heater patch panel transition board schematic [143]
6026-v1 - Heater Controller - Heater driver Gerber plots [144]
6026-v1 - Heater Controller - Heater driver transition Gerber plots [145]
6026-v1 - Heater Controller - Heater patch panel Gerber plots [146]
6026-v1 - Heater Controller - Heater patch panel transition Gerber plots [147]
6026-v1 - Heater Controller - Heater driver front panel [148]
6026-v1 - Heater Controller - Heater driver transition front panel [149]
6026-v1 - Heater Controller - Heater patch panel front panel [150]
6026-v1 - Heater Controller - Heater patch panel transition front panel [151]
4080-v7 Master Control Board - Users manual [152]
4080-v7 Master Control Board - Register map [153]
3642-v1 - SLINK - Instalation Instructions [154]
3642-v1 - SLINK - Front view before modification [155]
3642-v1 - SLINK - Front view after modification [156]
3642-v1 - SLINK - Back view after modification [157]
4080-v7 Master Control Board - Schematic (with ECOs) [158]
4080-v7 Master Control Board - Gerber plots [159]
4080-v7 Master Control Board - Bill Of Materials [160]
2509-v1 Master Control Board - Synchronization Slave wiring [161]
4080-v7 Master Control Board - EEPROM Image file - mcb_v521.mcs [52]
4080-v7 Master Control Board - FPGA Image file - mcb_v521.bit [53]
4080-v7 Master Control Board - ECO list [162]
1380-v11 Vicor Filter Box - Description and Construction notes [163]
1380-v11 Vicor Filter Box - Operating and Service Manual [164]
4265-v1 Vicor Power Supply - Quick reference guide [165]
4674-v1 Vicor Power Supply - Hardware power supply sequencer [166]
6051-v1 AC Power Distribution Chassis - Hardware description [167]
1380-v11 Vicor Filter Box - Schematic [168]
1380-v11 Vicor Filter Box - Voltage Monitor Divider circuits [169]
1380-v11 Vicor Filter Box - Gerber plots [170]
1380-v11 Vicor Filter Box - Layers [171]
1380-v11 Vicor Filter Box - Bill Of materials [172]
6051-v1 AC Power Distribution Chassis - Schematic [173]
6051-v1 AC Power Distribution Control Chassis - Schematic [174]
6051-v1 AC Power Distribution Control Chassis - Cable [175]
1380-v11 Vicor Filter Box - Drawings [176]
1380-v11 Vicor Filter Box - Mounting details [177]
6051-v1 AC Power Distribution Chassis - Fabrication drawings [178]
2343-v4 Vicor Power Supplies - Power up diagnostics [179]
Mechanical
5771-v8 Mechanical spares as of 20th April 2012 - MS-Excel file [180]
Electronic
5771-v8 Electronic spares as of 7th November 2012 - MS-Excel file [181]
Detectors
(Pending)
768-v37 Vacuum Interface Board - User manual [182]
768-v37 Vacuum Interface Board - Technical Design Report [60]
768-v37 Vacuum Interface Board - CCD Position Mapping [183]
2454-v1 VIB WEST - General views [184]
2454-v1 VIB WEST - Top view [185]
2454-v1 VIB WEST - Bottom view [186]
3301-v1 VIB-EAST - Top view [187]
3301-v1 VIB-EAST - Bottom view [188]
2976-v2 VIB WEST - Schematic [189]
2978-v1 VIB WEST - Gerber plots [190]
2982-v1 VIB WEST - Layers [191]
3303-v1 VIB-EAST - Schematic [192]
3302-v1 VIB-EAST - Gerber plots [193]
3302-v1 VIB-EAST - edited solder mask - supercedes Gerber plots [194]
3302-v1 VIB-EAST - new bottom layer solder mask - supercedes Gerber plots [195]
2977-v3 Vacuum Interface Board - Checkout procedure [196]
2977-v3 VIB-WEST - Checkout worksheet [197]
2977-v3 VIB-EAST - Checkout worksheet [198]
MONSOON Orange Data Sheet [1] Rev 1.1
MNSN-AD-02-0001 Detector Head Electronics Architecture (DHE) [201]
MNSN-AD-02-0002 System Architecture [202]
MNSN-AD-03-0001 Operational Concepts Definition [203]
MNSN-AD-04-0001 Functional Performance Requirements [204]
MNSN-AD-08-0006 Glossary of terms [205] Rev 2.3
The DHE is what is generically called a controller. This interface level is governed by the MONSOON Interface Control Documents (ICD) level 7 and 8. These documents control the hardware interfaces of the system.
Orange - ICD 7.0 MNSN-AD-01-0006 DHE Backplane Definition [206] Rev 13.1
Orange - ICD 7.1 MNSN-AD-01-0013 Requirements for the MCB Image Buffer Module (IBM) [207] Rev 2.0
Orange - ICD 8.4 MNSN-AD-01-0008 NEWFIRM to MONSOON [208] Rev 1.0
MNSN-AD-10-0001 Master Documentation List [209] Rev 0
IMPORTANT NOTE:
Xilinx have released an end of life advisory for the Virtex-E FPGA component used in the MONSOON Orange architecture. A copy of the advisory can be found here [210]. Please consider your options for safeguarding against obsolescence.
The pages below provide access to detail information of the Orange hardware modules.
The hardware information is generally arranged as:
Hardware user manuals
Schematic diagrams
Assembly drawings
Layout packages
Bill of materials
Firmware loader products
Transition module components (Schematics, assembly drawings, layout packages, bill of materials)
Hardware test procedure documents
Note that to use this information for your own purposes (i.e. build it or use it as the basis of a new design) you must agree to the open source license agreement. The license terms can be found here [25].
MNSN-AD-08-0001 MCB Description Document [211] Rev 4.2
MNSN-EL-02-1401 MCB Front Panel Detail [212] Rev 1
MNSN-EL-04-0001 MCB Assembly [213] Rev -A-
MNSN-EL-04-0001 MCB Assembly [214] Rev 2
MNSN-EL-04-2001 MCB Schematic Diagram [215] Rev -A-
MNSN-EL-04-3001 MCB Layout Package [216] Rev -A2-
MNSN-EL-04-4001-018 MCB Bill Of Materials [217] Rev -A1-
MNSN-EL-10-0400-018 MCB Top Assembly [218] Rev -A-
Standard configuration
MNSN-EL-06-0071 MCB U20 Pixel FPGA - Fpga Loader [219] Rev 4.65 (mcbpixfpgav465.bit)
MNSN-EL-06-0071 MCB U26 Pixel FPGA - EEProm Loader [220] Rev 4.65 (McbPixFpgaV465.mcs)
MNSN-EL-06-0066 MCB U25 Sequencer FPGA - Fpga Loader [221] Rev 4.67 (mcbseqfpgav467.bit)
MNSN-EL-06-0066 MCB U22 Sequencer FPGA - EEProm Loader [222] Rev 4.67 (McbSeqFpgaV467.mcs)
Specific to QUOTA
MNSN-EL-06-0060 MCB U25 Sequencer FPGA - Fpga Loader [223] Rev 4.92 (McbSeqFpgaV492.bit)
MNSN-EL-06-0060 MCB U22 Sequencer FPGA - EEprom Loader [224] Rev 4.92 (McbSeqFpgaV492.mcs)
Specific to SLINK communications
MNSN-EL-06-0019 MCB U20 Pixel FPGA - Fpga Loader [225] Rev 4.62 (mcbpixfpgav462.bit)
MNSN-EL-06-0019 MCB U26 Pixel FPGA - EEProm Loader [226] Rev 4.62 (McbPixFpgaV462.mcs)
MNSN-EL-06-0018 MCB U25 Sequencer FPGA - Fpga Loader [227] Rev 4.62 (mcbseqfpgav462.bit)
MNSN-EL-06-0018 MCB U22 Sequencer FPGA - EEProm Loader [228] Rev 4.62 (McbSeqFpgaV462.mcs)
MNSN-TS-01-0003 MCB Testing Procedure [229] Rev 0
Image Buffer Schematic Diagram [230]
MNSN-AD-01-0013 ICD 7.1 Image Buffer Module Requirements [231] Rev 2
Systran SL100 SL240 Catalog sheet [232]
Systran PCI Hardware reference manual [233]
Systran CMC Hardware reference manual [234]
Systran Flow control design note [235]
S-LINK MCB Hardware modifications [236]
S-LINK specifications [237]
S-LINK NOAO email to Miquel [238]
S-LINK FILAR Description [239]
S-LINK FILAR userguide [240]
S-LINK FILAR schematics [241]
S-LINK FILAR Bill of Materials [242]
S-LINK HOLA userguide [243]
S-LINK HOLA schematics [244]
S-LINK HOLA Bill of Materials [245]
MNSN-AD-08-0003 CBB Description [246] Rev 1.3
MNSN-EL-02-1301 CBB Front Panel Detail [247] Rev 1
MNSN-EL-04-0008 CBB Assembly [248] Rev 2
MNSN-EL-04-0008 CBB Assembly [249] Rev -A-
MNSN-EL-04-2008 CBB Schematic Diagram [250] Rev 1
MNSN-EL-04-2008 CBB Schematic Diagram [251] Rev A1
MNSN-EL-04-2008-003 CBB NEWFIRM Schematic Diagram [252] Rev 2
MNSN-EL-04-2008-007 CBB DECAM Schematic Diagram [253] Rev 2
MNSN-EL-04-3008 CBB Layout Package [254] Rev -A-
MNSN-EL-04-4008-017 CBB Bill of Materials [255] Rev A2
MNSN-EL-04-4008-001 CBB Bill of Materials [256] Rev 3
MNSN-EL-04-4008-001 CBB Bill of Materials [257] Rev 4
MNSN-EL-04-4008-003 CBB NEWFIRM Bill of Materials [258] Rev 3
MNSN-EL-10-0300-017 CBB Top Assembly [259] Rev -A-
MNSN-EL-10-0300-003 CBB NEWFIRM Top Assembly [260] Rev 2
MNSN-EL-10-0300-007 CBB DECAM Top Assembly [261] Rev 1
Standard configuration
MNSN-EL-06-0034 CBB U118 Sequencer CPLD - Cpld Loader [262] Rev 4.01 (ClkBiasSeqCpldV401.jed)
MNSN-EL-06-0061 CBB U119 Configuration CPLD - Cpld Loader [263] Rev 4.30 (ClkBiasCfgCpldV43.jed)
MNSN-EL-06-0067 CBB U116 FPGA - Fpga Loader [264] Rev 4.40 (ClkBiasFpgaV44.bit)
MNSN-EL-06-0067 CBB U200 FPGA - EEProm Loader [265] Rev 4.40 (ClkBiasFpgaV44.mcs)
Specific to QUOTA
MNSN-EL-06-0062 CBB U116 FPGA - Fpga Loader [266] Rev 4.92 (ClkBiasFpgaV492.bit)
MNSN-EL-06-0062 CBB U200 FPGA - EEProm Loader [267] Rev 4.92 (ClkBiasFpgaV492.mcs)
MNSN-EL-04-0007 CBB Transition ORION Test Set Assembly [268]
MNSN-EL-04-0010 CBB Transition Generic Assembly [269] Rev 1
MNSN-EL-04-0010 CBB Transition Generic Assembly [270] Rev -A-
MNSN-EL-04-0016 CBB Transition QUOTA Assembly [271] Rev -OD-
MNSN-EL-04-2007 CBB Transition ORION Test Set Schematic Diagram [272]
MNSN-EL-04-2010 CBB Transition Generic Schematic Diagram [273] Rev 1
MNSN-EL-04-2010 CBB Transition Generic Schematic Diagram [274] Rev -A-
MNSN-EL-04-2016 CBB Transition QUOTA Schematic Diagram [275] Rev -OD-
MNSN-EL-04-4007 CBB Transition ORION Test Set Bill Of Materials [276] Rev 1
MNSN-EL-04-4010 CBB Transition Generic Bill of Materials [277] Rev 2
MNSN-EL-04-4010 CBB Transition Generic Bill of Materials [278] Rev -A-
MNSN-EL-04-4016 CBB Transition QUOTA Bill of Materials [279] Rev 1
MNSN-EL-04-3007 CBB Transition ORION Layout Package [280] Rev 1
MNSN-EL-04-3010 CBB Transition Generic Layout Package [281] Rev -A-
MNSN-EL-04-3016 CBB Transition QUOTA Layout Package [282] Rev -0D-
NFM-EL-04-0006 CBB Transition NEWFIRM Assembly [283] Rev 1
NFM-EL-04-2006 CBB Transition NEWFIRM Schematic Diagram [284] Rev 1
NFM-EL-04-4006 CBB Transition NEWFIRM Bill of Materials [285] Rev 1
MNSN-TS-01-0004 CBB Testing Procedure [286] Rev 2
MNSN-AD-08-0002 IR Acquisition Board Description Rev 0 - Pending revision
MNSN-EL-02-1101 IRACQ Front Panel Detail [287]
MNSN-EL-02-1102 IRACQ Front Panel Detail [288] Rev 1
MNSN-EL-04-0004 IRACQ Motherboard Assembly [289] Rev -A1-
MNSN-EL-04-0004 IRACQ Motherboard Assembly [290] Rev -B-
MNSN-EL-04-0005 IRACQ Daughterboard Assembly [291] Rev -B-
MNSN-EL-04-0005 IRACQ NEWFIRM Daughterboard Assembly [292] Rev -A-
MNSN-EL-04-2004 IRACQ Motherboard Schematic Diagram [293] Rev -A1-
MNSN-EL-04-2004 IRACQ Motherboard Schematic Diagram [294] Rev -B-
MNSN-EL-04-2005 IRACQ Daughterboard Schematic Diagram [295] Rev -A-
MNSN-EL-04-2005 IRACQ Daughterboard Schematic Diagram [296] Rev -B-
MNSN-EL-04-3004 IRACQ MotherBoard Layout Package [297] Rev -B-
MNSN-EL-04-3005 IRACQ Daughterboard Layout Package [298] Rev -B-
MNSN-EL-04-4004-001 IRACQ Motherboard Bill of Material [299] Rev -A1-
MNSN-EL-04-4004-010 IRACQ Motherboard Bill of Materials [300] Rev -B-
MNSN-EL-04-4005-001 IRACQ Daughterboard Bill of Materials [301] Rev -A1-
MNSN-EL-04-4005-010 IRACQ Daughterboard Bill of Materials [302] Rev -B-
MNSN-EL-10-0100-001 IRACQ NEWFIRM Top Assembly [303] Rev -A1-
MNSN-EL-10-0100-010 IRACQ Top Assembly [304] Rev -B-
Revision -A- Hardware
MNSN-EL-06-0069 IRACQ U55 FPGA - Fpga Loader [305] Rev 4.16 (IrAcqFpgaV416.bit)
MNSN-EL-06-0069 IRACQ U95 FPGA - EEProm Loader [306] Rev 4.16 (IrAcqFpgaV416.mcs)
MNSN-EL-06-0026 IRACQ CPLDS - Cpld Loader [307] Rev 4.00 (IRAcqCpldV40.jed)
Revision -B- Hardware
MNSN-EL-06-0070 IRACQ U20 FPGA - Fpga Loader [308] Rev 4.21 (iracqfpgav421.bit)
MNSN-EL-06-0070 IRACQ U95 FPGA - EEProm Loader [309] Rev 4.21 (IrAcqFpgaV421.mcs)
MNSN-EL-06-0058 IRACQ CPLDS - Cpld Loader [310] Rev 4.10 (IrAcqCpldV41.jed)
MNSN-EL-04-0012 IRACQ Transition WHIRC Top Assembly [311] Rev -A-
MNSN-EL-04-0012 IRACQ Transition WHIRC Readme [312] Rev -A-
MNSN-EL-04-1012 IRACQ Transition WHIRC Assembly [313] Rev -A-
MNSN-EL-04-2012 IRACQ Transition WHIRC Schematic Diagram [314] Rev -A-
MNSN-EL-04-3012 IRACQ Transition WHIRC Layout Package [315] Rev -A-
MNSN-EL-04-4012 IRACQ Transition WHIRC Bill of Materials [316] Rev -A-
MON3000-0053 IRACQ Transition ORION Test Set Schematic Diagram [317] Rev 1
MON3000 0054 IRACQ Transition ORION Test Set Assembly [318] Rev 1
MON3000 0055 IRACQ Transition ORION Test Set Bill of Materials [319] Rev 1
NFM-EL-04-0005 IRACQ Transition NEWFIRM Assembly [320] Rev 1
NFM-EL-04-2005 IRACQ Transition NEWFIRM Schematic Diagram [321] Rev 1
NFM-EL-04-4005 IRACQ Transition NEWFIRM Bill of Materials [322] Rev 1
MNSN-TS-01-0005 IRACQ Acquisition Board Testing [323] Rev 0
MNSN-AD-08-0004 CCDACQ Description [324] Rev 1.2
MNSN-EL-02-1501 CCDACQ Front Panel Detail [325] Rev 1
MNSN-EL-04-0002 CCDACQ Assembly [326] Rev -B-.
MNSN-EL-04-1002 CCDACQ Fabrication detail [327] Rev -B-
MNSN-EL-04-2002 CCDACQ Schematic Diagram [328] Rev -B1-
MNSN-EL-04-3002 CCDACQ Layout Package [329] Rev -B4-
MNSN-EL-04-4002 CCDACQ Bill of Materials [330] Rev -B2-
Standard configuration
MNSN-EL-06-0052 CCDACQ CPLD - Cpld Loader [331] Rev 4.10 (ccdAcqCpldV41.jed)
MNSN-EL-06-0068 CCDACQ U68 FPGA - Fpga Loader [332] Rev 4.12 (ccdacqfpgav412.bit)
MNSN-EL-06-0068 CCDACQ U143 FPGA - EEProm Loader [333] Rev 4.12 (ccdacqfpgav412.mcs)
Specific to QUOTA
MNSN-EL-06-0063 CCDACQ U68 FPGA - Fpga Loader [334] Rev 4.95 (ccdacqfpgav495.bit)
MNSN-EL-06-0063 CCDACQ U143 FPGA - EEProm Loader [335] Rev 4.95 (ccdacqfpgav495.mcs)
MNSN-EL-04-0009 CCDACQ Transition Generic Assembly [336] Rev 1
MNSN-EL-04-0015 CCDACQ Transition QUOTA Assembly [337] Rev -OD-
MNSN-EL-04-2009 CCDACQ Transition Generic Schematic Diagram [338] Rev 1
MNSN-EL-04-2015 CCDACQ Transition QUOTA Schematic Diagram [339] Rev -OD-
MNSN-EL-04-3009 CCDACQ Transition Generic Layout Package [340] Rev 1
MNSN-EL-04-3015 CCDACQ Transition QUOTA Layout Package [341] Rev -0D-
MNSN-EL-04-4009 CCDACQ Transition Generic Bill of Materials [342] Rev 2
MNSN-EL-04-4015 CCDACQ Transition QUOTA Bill of Materials [343] Rev 1
MNSN-TS-01-0002 CCDACQ Testing Procedures [344] Rev 3.1
This board is used to connect the Orange transition modules to the analog power sources. This power penetrates the Orange backplane via connector P3 and is independent of the backplane power system. The available designs provide for a right and left handed distribution that corresponds to the position of the bus master slot (MCB slot).
Left Hand Variant
MNSN-EL-04-0003 PWRFAN Left Hand Top Assembly [345]
MNSN-EL-04-1003 PWRFAN Left Hand Fabrication Detail [346]
MNSN-EL-04-2003 PWRFAN Left Hand Schematic Diagram [347]
MNSN-EL-04-3003 PWRFAN Left Hand Layout Package [348]
Right Hand Variant
MNSN-EL-04-0006 PWRFAN Right Hand Top Assembly [349] Rev -A-
MNSN-EL-04-1006 PWRFAN Right Hand Fabrication Detail [350] Rev -A-
MNSN-EL-04-2006 PWRFAN Right Hand Schematic Diagram [351] Rev -A-
MNSN-EL-04-3006 PWRFAN Right Hand Layout Package [352] Rev -A-
The MONSOON Orange system does not specify a specific power supply solution since it is designed as an expandable system. By definition this precludes having a single power supply design. However, there is one power supply solution that have been used successfully at NOIRLab. The following files give information about the 30 Watt 'Wall Mount' supply..
30 Watt 'Wall Mount' power supply - Suitable for a minimal CCD system in a 4-slot or 6-slot chassis.
MNSN-EL-05-0003 Power Supply Chassis Wiring Diagram [353] Rev -B-
MNSN-EL-05-0004 Power Supply Cables [354] Rev -B-
MNSN-EL-05-0014 Power Supply Wall Mount [355] Rev 1
MNSN-EL-05-0015 Power Supply Wall Mount Wiring List [356] Rev -OD-
MNSN-EL-02-0011 Power Supply Wall Mount Bill of Materials [357] Rev -OD-
MNSN-EL-02-1016 Power Supply Wall Mount Delay Board Fabrication Detail [358]
Chassis wiring is dependent on the physical implementation details. The documents given here are representative of the wiring we use at NOIRLab to achieve optimum performance from the system. They may be used as a reference for future designs.
MNSN-EL-05-0002 Chassis Wiring Diagram With Terminal Blocks [359]
MNSN-EL-05-0005 Chassis Wiring Diagram With Out Terminal Blocks [360] Rev -A-
MNSN-EL-05-0008 Chassis Wiring Grounding Scheme Bench Spectrograph [361] Rev -OD-
MNSN-AD-08-0005 MONSOON Software Setup [362] Rev 2.1
MON-0000-0016 PAN Software Design Document [363] Rev 1.0
MON-0000-0016 PAN Software Design Note [364] Rev 1.0
MONSOON Library API [365] Rev 1.0
MONSOON Supervisor Layer Software Design [366]
MNSN-AD-08-0010 Operating Instructions for WIYN Bench Spectrograph [367] Rev 2
MNSN-AD-08-0011 Operating Instructions for QUOTA [368] Rev 0
MONSOON Orange Assembler [369] Rev 4.0
MONSOON Orange Assembler [370] Rev 5.0
MONSOON Orange Assembler [371] Rev 6.0
DownLoad link - Removed since server died, please contact technical representative
DownLoad link - Removed since server died, please contact technical representative
MNSN-EL-06-9500 FIRMWARE Quick Guide [372] Rev 1.8
MNSN-EL-06-9500 FIRMWARE History [373]
MONSOON Existing Firmware Products [374] as at 20080827
Master Control Board (MCB)
MNSN-EL-06-0018 MCB Source McbSeqFpgaV462 [375] Rev 4.62
MNSN-EL-06-0060 MCB Source McbSeqFpgaV492 [376] Rev 4.92
MNSN-EL-06-0065 MCB Source McbSeqFpgaV465 [377] Rev 4.65
MNSN-EL-06-0066 MCB Source McbSeqFpgaV467 [378] Rev 4.67
MNSN-EL-06-0019 MCB Source McbPixFpgaV462 [379] Rev 4.62
MNSN-EL-06-0064 MCB Source McbPixFpgaV464 [380] Rev 4.64
MNSN-EL-06-0071 MCB Source McbPixFpgaV465 [381] Rev 4.65
Clock and Bias Board (CBB)
MNSN-EL-06-0034 CBB Source ClkBiasSeqCpldV401 [382] Rev 4.01
MNSN-EL-06-0037 CBB Source ClkBiasFpgaV42 [383] Rev 4.20
MNSN-EL-06-0061 CBB Source ClkBiasCfgCpldV43 [384] Rev 4.30
MNSN-EL-06-0062 CBB Source ClkBiasFpgaV492 [385] Rev 4.92
MNSN-EL-06-0067 CBB Source ClkBiasFpgaV44 [386] Rev 4.40
IR Acquisition Board (IRACQ)
MNSN-EL-06-0026 IRACQ REV -A- ALL CPLDS Source IRAcqCpldV40 [387] Rev 4.00
MNSN-EL-06-0027 IRACQ REV -A- Source IRAcqFpgaV413 [388] Rev 4.13
MNSN-EL-06-0069 IRACQ REV -A- Source IRAcqFpgaV416 [389] Rev 4.16
MNSN-EL-06-0058 IRACQ REV -B- ALL CPLD Source IRAcqCpldV41 [390] Rev 4.10
MNSN-EL-06-0028 IRACQ REV -B- Source IRAcqFpgaV42 [391] Rev 4.20
MNSN-EL-06-0070 IRACQ REV -B- Source IRAcqFpgaV421 [392] Rev 4.21
CCD Acquisition Board (CCDACQ)
MNSN-EL-06-0052 CCDACQ Source CcdAcqCpldV41 [393] Rev 4.10
MNSN-EL-06-0063 CCDACQ Source CcdAcqFpgaV495 [394] Rev 4.95
MNSN-EL-06-0068 CCDACQ Source CcdAcqFpgaV412 [395] Rev 4.12
Templates
Template - Bus Interface [396]
Template - Personality Module [397]
MNSN-EL-02-0005 Extraction Tool Assembly [398]
MNSN-EL-02-1008 Extraction Tool Detail [399]
MNSN-EL-02-0007 Power Supply Chassis Assembly Drawing [400]
MNSN-EL-02-0008 Power Supply Chassis Bill of Materials [401]
MNSN-EL-02-0011 Power Supply Chassis Bill of Materials [402] Rev -OD-
MNSN-EL-02-1011 Power Supply Chassis Detail Front Panel Modification [403]
MNSN-EL-02-1012 Power Supply Chassis Detail Side Panel Modifications [404] Rev 2
MNSN-EL-02-1013 Power Supply Chassis Detail Back Panel Modifications [405]
MNSN-EL-02-1014 Power Supply Chassis Detail Shelf Modifications [406]
MNSN-EL-02-1015 Power Supply Chassis Detail Cover Modifications [407]
MNSN-EL-02-1016 Power Supply Chassis Detail Delay and Resistor Board [408]
MNSN-EL-02-0003 6-Slot Generic Assembly Drawing [409]
MNSN-EL-02-0004 6-Slot Generic Parts List [410]
MNSN-EL-02-0006 6-Slot FHIRE Parts Lis [411]t
MNSN-EL-02-1003 6-Slot Generic Detail Panel Left Side Modification [412] Rev -A-
MNSN-EL-02-1010 6-Slot Generic Detail Label TBLK Arrangement [413]
MNSN-EL-02-1017 6-Slot Generic Detail Mounting Bracket Dual Fan [414]
MNSN-EL-02-1018 6-Slot Generic Detail Temporary Back Panel [415] Rev -A-
MNSN-EL-02-1019 6-Slot Generic Detail Panel Right Side Modification [416]
MNSN-EL-02-1020 6-Slot Generic Detail Horizontal Rail Modification [417] Rev -A-
MNSN-EL-02-1021 6-Slot Generic Detail Threaded and Insulation Strip Modifications [418] Rev -A-
MNSN-EL-02-1059 6-Slot Chassis Detail Rear Panel [419] Rev -OD-
MNSN-EL-02-1060 6-Slot Chassis Detail Front Panel [420] Rev -A-
MNSN-EL-02-0002 12-Slot Generic Parts List [421]
MNSN-EL-02-0004 12-Slot Generic Detail Mounting Rails Power Supply [422]
MNSN-EL-02-1001 12-Slot Generic Detail Fan Exhaust [423]
MNSN-EL-02-1002 12 Slot Generic Detail Rail G-10 Cage [424]
MNSN-EL-02-1004 12-Slot Chassis Detail Chassis Support Bar [425]
MNSN-EL-02-1005 12-Slot Generic Detail Mounting Plate Power Supply Filters [426]
MNSN-EL-02-1006 12-Slot Generic Detail Inner Side Panel With Fan Cutout [427]
MNSN-EL-02-1007 12-Slot Generic Detail Outer Side Panel With Fan Cutout [428]
MNSN-EL-02-1009 12-Slot Generic Detail Horizontal Rail Card Cage [429]
These system configuration data packages can be used as templates for future instrument configuration sets. They are offered 'as is' without any warranty as to their operational state or suitability of purpose to other implementations.
Configuration _bert [430] - Used as a test bed for various testing schemes.
Configuration _ccdBrdTest [431] - Facilitates testing of the CCDACQ board hardware
Configuration _clkBrdTest [432] - Facilitates testing of the CBB hardware
Configuration _fred [433] - Generic 'always works' test bed for system development
Configuration _iracqBrdTest [434] - Facilitates testing the IRACQ board hardware
Configuration _labTest [435] - Laboratory test system configuration
Configuration _mcbBrdTest [436] - Facilitates testing the MCB hardware
Configuration _mnsnBrdTest [437] - For use with the board test software
Configuration _mosaic1 [438] - Configuration code running 8 E2V detectors at prime focus on Mayall telescope.
Configuration _NEWFIRM_Tucson [439] - Current 4k x 4k IR imager configuration data set
Configuration _ota [440] - Used to characterize the OTA detectors during development for the WIYN ODI instrument
Configuration _pcmTest [441] - My own personal 'I trust this' configuration data set
Configuration _qGde [442] - ??
Configuration _quota [443] - WIYN QUOTA focal plane configuration for science readout
Configuration _quota_guide [444] - WIYN QUOTA focal plane setup optimized for fast guiding role
Configuration _tom [445] - General purpose test system (early).
Torrent Data Sheet [2] Rev 4.1
TRNT-AD-11-0001 Torrent DHE Architecture [446] Rev 5.0
TRNT-AD-11-0001 Torrent Performance Requirements [447] Rev 0.0
TRNT-AD-04-0001 Torrent DHE Compliance Tests [448] Rev 2.5
TRNT-AD-04-0002 Report on Torrent DHE Compliance Tests [449] Rev 1.0
The DHE is what is generically called a controller. This interface level is governed by the MONSOON Interface Control Documents (ICD) level 7 and 8. These documents control the hardware interfaces of the system.
Torrent - ICD 7.? TRNT-AD-01-0001 AFE-CCD Circuit Board Dimensions [450] Rev -OD-
Torrent - ICD 7.3 TRNT-AD-01-0003 Torrent DHE LCB to AFE Interface Description [451] Rev 0.0
Torrent - ICD 7.4 TRNT-AD-01-0004 Torrent DHE PSM to LCB Interface Description [452] Rev 0.0
Torrent - ICD 7.6 TRNT-AD-01-0006 Torrent DHE PSM to TSM Interface Description [453] Rev 0.0
Torrent User Survey [454] Rev 4 - Used to specify the details of a buildable configuration for a Torrent DHE
TRNT-AD-10-0001 Master Documentation List [455] Rev 0
The relationship between the various hardware modules of the Torrent DHE is shown here [456] in the DHE interconnect diagram.
The controlled grounding scheme for the Torrent DHE can be found here [457]
Torrent DHE Hardware Description Guide - Covers all Torrent electronics.
TRNT-AD-08-0007 DHE Hardware Description [458] Rev 1.1
The pages below provide access to the schematic and assembly information of the Torrent hardware modules.
The information on these pages is generally arranged as:
Assembly drawings
Schematic diagrams
Layout packages
Bill of materials
Firmware loader products
Testing Procedures
Note that to use this information for your own purposes (i.e. build it or use it as the basis of a new design) you must agree to the open source license agreement. The license terms can be found here [25].
Local Control Board
TRNT-EL-04-0002 LCB Top Assembly [459] Rev -B-
TRNT-EL-04-1002 LCB Fabrication Detail [460] Rev -B-
TRNT-EL-04-2002 LCB Schematic Diagram [461] Rev -B-
TRNT-EL-04-3002 LCB Layout Package [462] Rev -B-
TRNT-EL-04-4002 LCB Bill of Materials [463] Rev -B-
Firmware Loader Products
TRNT-EL-06-0001 LCB FPGA - Fpga Loader [464] Rev 2.22 (torrentfpga_ver222.bit)
TRNT-EL-06-0001 LCB FPGA - EEprom Loader [465] Rev 2.22 (torrentfpga_ver222.mcs)
LCB Testing Procedures
TRNT-TS-01-0003 LCB Test Procedure [466] Rev 0
TRNT-EL-04-0003 LCB-MEZ Top Assembly [467] Rev -A3-
TRNT-EL-04-1003 LCB-MEZ Fabrication Detail [468] Rev -A-
TRNT-EL-04-2003 LCB-MEZ Schematic Diagram [469] Rev -A4-
TRNT-EL-04-3003 LCB-MEZ Layout [470] Rev -A-
TRNT-EL-04-3003 LCB-MEZ Layout Package [470] Rev -A-
TRNT-EL-04-4003 LCB-MEZ Bill of Materials [471] Rev -A5-
TRNT-EL-04-0001 PSM Top Assembly [472] Rev -B-
TRNT-EL-04-1001 PSM Fabrication Detail [473] Rev -B-
TRNT-EL-04-2001 PSM Schematic Diagram [474] Rev -B-
TRNT-EL-04-3001 PSM Layout Package [475] Rev -B-
TRNT-EL-04-4001 PSM Bill of Materials [476] Rev -B-
CCD Analog Front End
TRNT-EL-04-0004 AFE-CCD Top Assembly [477] Rev -C-
TRNT-EL-04-1004 AFE-CCD Fabrication Detail [478] Rev -C-
TRNT-EL-04-2004 AFE-CCD Schematic Diagram [479] Rev -C1-
TRNT-EL-04-3004 AFE-CCD Layout [480] Rev -C1-
TRNT-EL-04-4004 AFE-CCD Bill of Materials [481] Rev -C1-
Analog Front End Calibration Worksheet
AFE-CCD Calibration Worksheet [482]
Analog Front End Extender Board
TRNT-EL-04-0008 AFE-EXT Circuit Board Dimensions [483] Rev -OD-
TRNT-EL-04-1008 AFE-EXT Fabrication Detail [484] Rev -OD-
TRNT-EL-04-2008 AFE-EXT Schematic Diagram [485] Rev -0D-
TRNT-EL-04-3008 AFE-EXT Layout [486] Rev -OD-
Analog Front End Testing Procedures
TRNT-TS-01-0004 AFE-CCD Test Procedure [487] Rev 0
Transition Module Preamplifier for CCD (TSM-CCD)
TRNT-EL-04-0007 TSM-CCD Top Assembly [488] Rev -C1-
TRNT-EL-04-1007 TSM-CCD Fabrication Detail [489] Rev -C-
TRNT-EL-04-2007 TSM-CCD Schematic Diagram [490] Rev -C1-
TRNT-EL-04-4007 TSM-CCD Bill of Materials [491] Rev -C1-
TRNT-EL-04-0007 TSM-CCD Top Assembly [492] Rev -B-
TRNT-EL-04-1007 TSM-CCD Fabrication Detail [493] Rev -B-
TRNT-EL-04-2007 TSM-CCD Schematic Diagram [494] Rev -B-
TRNT-EL-04-3007 TSM-CCD Layout [495] Rev -B-
TRNT-EL-04-4007 TSM-CCD Bill of Materials [496] Rev -B-
Transition Module Utility Board (TSM-UTIL)
TRNT-EL-04-0009 TSM-UTIL Top Assembly [497] Rev -A1-
TRNT-EL-04-1009 TSM-UTIL Fabrication Detail [498] Rev -A-
TRNT-EL-04-2009 TSM-UTIL Schematic Diagram [499] Rev -A2-
TRNT-EL-04-3009 TSM-UTIL Layout [500] Rev -A-
TRNT-EL-04-3009 TSM-UTIL Layout Package [501] Rev -A-
TRNT-EL-04-4009 TSM-UTIL Bill of Materials [502] Rev -A4-
Transition Module Utility Board Testing Procedures
TRNT-TS-01-0005 TSM-UTIL Test Procedure [503] Rev 0
Video Flex
TRNT-EL-04-0005 CCD-FLEX-VID Top Assembly [504] Rev -A-
TRNT-EL-04-1005 CCD-FLEX- [505]VID [504] Fabrication Detail [505] Rev -A-
TRNT-EL-04-2005 CCD-FLEX- [506]VID [504] Schematic Diagram [506] Rev -A-
TRNT-EL-04-3005 CCD-FLEX- [507]VID [504] Layout Package [507] Rev -A-
Clock and Bias Flex
TRNT-EL-04-0006 CCD-FLEX-CB Top Assembly [508] Rev -A-
TRNT-EL-04-1006 CCD-FLEX-CB Fabrication Detail [509] Rev -A-
TRNT-EL-04-2006 CCD-FLEX- [510]CB [508] Schematic Diagram [510] Rev -A-
TRNT-EL-04-3006 CCD-FLEX- [511]CB [508] Layout [511] Rev -A-
TRNT-EL-03-0001 CBL PSM to TSM-UTIL Connector [512]
TRNT-EL-03-0002 CBL TSM-UTIL to Shutter and Preflash Connector [513]
TRNT-EL-03-0003 CBL GIGe Ethernet Shield Wire [514]
TRNT-EL-03-0006 CBL TSM Chassis Ground Wire [515]
MONSOON/Torrent Software Setup Guide
MNSN-AD-08-0005 MONSOON Software Setup Guide [516] Rev 2.1
Torrent Software Description
TRNT-AD-08-0001 Torrent Software System Description [517] Rev 0
Acquisition Software Client
TRNT-AD-08-0002 borg and mborg clients [518] Rev 0
System Configuration Tools
TRNT-AD-08-0006 Software User Manual [519] Rev 0
Attribute Extraction Tool
TRNT-AD-08-0003 Assimilate [520] Rev 1.2
Attribute Collector Tool
TRNT-AD-08-0004 Collector [521] Rev 1.1
Torrent Sequencer description
TRNT-AD-08-0012 Torrent Sequencer Description [522] Rev 0
Sequencer Assembler
Torrent assembler [523] Rev 6.0
The calibration EEPROMs for Torrent systems are contained on each of the component electronics boards. A fully populated Torrent system will have five Calibration EEPROMs, four in the Controller box and one in the TSM box. There is one EEPROM on the LCB, one on the PSM and one on each of the AFE boards.
These EEPROMs are currents arranged as 128 pages of 16 words each 32 bits wide. Pages 0 and 1 are ID pages that contain information to identify and help verify the data stored in the EEPROM.
Data stored in the EEPROMS is all integer values. Where a floating point value is desired we store the value as int( value * 1000 ) This limits the range of values that can be stored to -2,147,483.000 to 2,147,483.000. We could not think of any requirement that required a greater range
A copy of the data in the EEPROMs for each system is kept in a set of EEPROM Mirror Files stored in the $MONSOON_CFG/_sysName configuration directory for the system. Changing out a DHE Controller will require obtaining the correct mirror files for the new controller from the Torrent configuration database
| Word # | Word Name | Board | Default Value | Long Name | Comments |
|---|---|---|---|---|---|
| 0 | PSTORFORMAT | ALL | 0x00000001 | EEPROM Storage Format | The Code for the Format of the data stored in this EEPROM (1) |
| 1 | MDLIDCODE | LCB | 0x00000010 | Module ID Code | The code number assigned to the LCB boards (16) |
| PSM | 0x00000020 | The code number assigned to the PSM boards (32) | |||
| CCD AFE | 0x00000040 | The code number assigned to the CCD AFE boards (64) | |||
| IR AFE | 0x00000050 | The code number assigned to the IR AFE boards (80) | |||
| TSM Utility | 0x00000030 | The code number assigned to the IR AFE boards (48) | |||
| 2 | MDLVARCODE | ALL | 0x00000001 | Module Variant Code | The Variant ## of a board that differs from a standard board (1) |
| 3 | MDLREVNUM | ALL | 0x00000001 | Module Release Number | The release number for the module being read all still at release 1 |
| 4 | MDLSERNUM | ALL | 0x0000xxxx | Module Serial number | The serial number of this board. Currently not in use |
| 5 | SYSFPGACODE | ALL | 0x000000CC | System FPGA Code Version | The FPGA code version used to write this EEPROM Currently 204 |
| 6 - 15 | Not Used | ALL | 0x00000000 | Not Used | Locations Reserved |
| Word # | Word Name | Board | Default Value | Long Name | Comments |
|---|---|---|---|---|---|
| 0 | MDLLASTTESTDATE | ALL | 20090316 | Module's Last Test Date | The date of the last time this board was tested (various) |
| 1 | LASTWRTDATE | ALL | 20110318 | EEPROM Last Written Date | The date of the last time this EEPROM was written (various) |
| 2 | VLDPAGECNT | ALL | 0x00000005 | Valid Page Count | The number of pages in the EEPROM that contain Valid Data (various) |
| 3 - 11 | Not Used | ALL | 0x00000000 | Not Used | Locations Reserved |
| 12 - 15 | CRC0 - CRC3 | ALL | 7FE163FB6 | CRC code portion 0 - 3 | The 128 byte representation of the MD5Sum calculated on the Data in all valid pages excepting Page 1 words 12 through 15 (various) |
This is a basic guide to setting up a system configuration from scratch ...
In big-boy
1. run bldMNSN
to setup distribution directory structure
2. run assimilate -version 207 -sysName mySystemName
-version points to the version of firmware that is in the hardware -sysName points to a common directory of form /MNSN/soft_dev/cfg/_mySystemName/.dscFiles and /MNSN/soft_dev/cfg/_mySystemName/.eep which are used to contain the Torrent specific configuration files
3. run arrayDesc -type genericdetectorType -arrayID thisDetectorName -fpName mySystemName for as many detectors that make up the focal plane, changing the -arrayID value for each one.
-type identifies a generic detector description
currently available types are
e2v44-82
e2v231-84
lbnl234
STA1042
-arrayID is the unique identifier for this detector, usually the serial number or a positional key
-fpName is the system configuration name
see file big-boy:/MNSN/soft_dev/Torrent_Text/sysName.ini.tmplt
The values in the template file will be replaced by the "collector" with values read from the system TSM eeprom
see file big-boy:/MNSN/soft_dev/Torrent_Text/sysName_DefaultSetup.mod.tmplt
The values in the template file will be replaced by the "collector" with values read from the system TSM eeprom.
Reading out Regions of Interest (ROI) for CCD focal planes can be extremely complex. The inter-connection between number of outputs per detector, number and orientation of detectors and pixel binning can result in scenarios that are too complex for the simple sequencer processing available in MONSOON/Torrent systems.
Four user attributes are used to describe a region of interest. These attributes are all described by pixel positions or counts given assuming no binning is being done. The values loaded down to the sequencer are modified to take into account any requested binning values.
The following explains the restrictions on ROI definitions made to simplify ROI handling to prevent some of this complication.
There are sixteen 16-bit loop registers for available in the Sequencer to enable code flow control. The table below shows their current default usage. While these registers are general purpose loop registers using them for other than their reserved purpose will require the writing of a custom Detector library routine (detCalcPixels) to load the registers with correct values before taking an image.
The generic_CCD and basciCCD detector libraries use these assignments, but load the seqColBin register with one less than the requested number of pixels to be binned and sets the user Bit serBinEnbl to 1 if serial binning is active. The chileCCD detector library uses these assignments, and loads the seqColBin register with the requested number of pixels to be binned and does not use serBinEnbl user bit.
| Register number | FPGA Register name | CCD User Register name | CCD Sequencer Usage | IR User Register name | IR Sequencer Usage | Comments |
|---|---|---|---|---|---|---|
| 0 | SeqLoopReg[0] | seqRowCount | #NROW | seqRowCount | #ROW_CNT | Number of rows to readout i.e. for CCDs the number of parallel or slow shifts |
| 1 | SeqLoopReg[1] | seqColCount | #NCOL | seqColCount | #COL_CNT | Number of columns to readout i.e. for CCDs the number of serial or fast shifts |
| 2 | SeqLoopReg[2] | seqRowBin | #NPBINS | seqFSamples | #FSAMPLES | Number of rows to bin during CCD readout or number of Fowler samples in IR Readout |
| 3 | SeqLoopReg[3] | seqColBin | #NSBINS | seqDigAvg | #DIG_AVG | Number of columns to bin during CCD readout or number of Digital Average samples in IR Readout |
| 4 | SeqLoopReg[4] | seqRoiRow | #ROIROW | seqCoAdds | #COADDS | Number of rows to skip during CCD ROI readout or number of Co-Adds in IR Readout |
| 5 | SeqLoopReg[5] | seqRoiCol | #ROICOL | seqLoopDly | #LOOP_DLY | Number of columns to skip during CCD ROI readout or read loop delay factor in Fowler IR Readout |
| 6 | SeqLoopReg[6] | seqRoiRskip | #RROWSKP | seqSweeps | #SWEEPS | Number of rows to skip after ROI readout is Complete or number of reset cycles before integration in IR mode |
| 7 | SeqLoopReg[7] | seqRoiCskip | #RCOLSKP | seqSyncResets | #SYNC_RESETS | Number of columns to skip on each row after the ROI columns are read out or number of resets to do when syncing two DHE's |
| 8 | SeqLoopReg[8] | seqFocusShft | #FOCUS_SHFT | seqRstTime | #RST_TIME | number of rows to shift image between focus exposures |
| 9 | SeqLoopReg[9] | seqPreScan | #XPRE | Not Assigned | Not Assigned | number of prescan pixels to read (Usually not converted or transferred to the PAN |
| 10 | SeqLoopReg[10] | seqShtrDly | #SHUTDLY | Not Assigned | Not Assigned | The time in ms to delay while the shutter opens or closes if these times are different use an unassigned register for the closing time. |
| 11 | SeqLoopReg[11] | OvrScanRowCnt | #OSROWCNT | Not Assigned | Not Assigned | Number of binned rows to convert after reading ROI rows and skipping unread active rows |
| 12 | SeqLoopReg[12] | OvrScanColCnt | #OSCOLCNT | Not Assigned | Not Assigned | Number of binned pixels to convert after reading ROI pixels skipping unread active pixels |
| 13 | SeqLoopReg[13] | Not Assigned | Not Assigned | Not Assigned | ||
| 14 | SeqLoopReg[14] | Not Assigned | Not Assigned | Not Assigned | ||
| 15 | SeqLoopReg[15] | Not Assigned | Not Assigned | Not Assigned |
The MONSOON/Torrent systems have in the sequencer Control register four user settable bits that can be used with The conditional jump instruction to steer the ucode execution. The following are the current default usage for these bits.
| User bit number | FPGA Attribute name | CCD User Attribute name | CCD Sequencer Usage | IR User Attribute name | IR Sequencer Usage | Comments |
|---|---|---|---|---|---|---|
| 0 | SeqUserBit0 | seqContRun | #CONT_RUN | seqContRun | #CONT_RUN | Debug function - run process indefinitely after start exposure received |
| 1 | SeqUserBit1 | serBinEnbl | #SBIN_ENB | Not Assigned | #IDLERST_ENBL | Enable serial binning in CCD readout or enable array resets during idle time for IR apps. |
| 2 | SeqUserBit2 | rdRoiEnbl | #RDROI_ENB | digAvgEnb | #DIGAVG_ENBL | Tells the sequencer a ROI readout is in progress for CCDs or enable digital averaging in IR apps. |
| 3 | SeqUserBit3 | Not Assigned | Not Assigned | Not Assigned | #ROWRST_ENBL | Enable Row Reset mode in IR apps. |
TRNT-AD-08-0010 Firmware Users Guide for Version 2.22 [524] Rev 2
TRNT-AD-08-0011 AFE Control Module Firmware Guide [525] Rev 0 - Needs updating !
Firmware Design Outline Torrent LCB Firmware Design [526] Rev -C3-
From Open-Cores. Wishbone Bus specification [527] Rev -B3-1-
Clock Generator Device Programming Clock Generation Workbook [528] Rev 4
AFE Serial device data format description Torrent Serial Device Control List [529]
Power Supply to Pixel Sychronization Power Supply Sync Analysis [530]
System Level
TRNT-EL-06-0001 TorrentFpga_Ver222 [531]
Module Level
AFE_Control_Ver221 [532]
CFG_Services_Ver220 [533]
CLK_Services_Ver221 [534]
DummyModule_Ver220 [535]
LCB_Control_Ver222 [536]
PIX_Services_Ver221 [537]
PSM_Services_Ver221 [538]
Templates
CmdDecodeFifo [539]
CommsDemuxPixBuffr_V106 [540]
I2C_InterfaceV100 [541]
I2C_Inerface_Ver210 [542]
PixDataMuxFifo_V103 [543]
SeqPatMemCore [544]
SeqProgMemCore [545]
SerialFPDP_fifo_5v5 [546]
SerialFPDPV5v5a - Contact Peter Moore (pmoore_at_noao.edu)
SerialFPDPV5V5b - Contact Peter Moore (pmoore_at_noao.edu)
SyncPortFifo_V100 [547]
Uart_8 [548]
UartFifo [549]
VideoFifo [550]
WishBoneIntercon_Ver222 [551]
WishBoneMasterInterfaceV106 [552]
WishBoneSlaveInterface_Ver207 [553]
NOAO_tblock [554]
There are four communication channels available on the Torrent DHE. The table below shows the available bandwidth for these links and their intended use.
| Channel | Bit Rate | Command Bandwith (32-bit Words) | Video Data Bandwith (18-bit Words) | Purpose |
|---|---|---|---|---|
| Systran | 1.0625 GBit/sec | 26.5 Meg/sec | 26.5 (53 for 16-bit packed pixels) Meg/sec | Primary command downlink, Primary data uplink. |
| Sync In/Out | 39.8 Meg/sec | 1.0 Meg/sec | n/a | Inter-DHE communications, commands, synchronization |
| UART | 9600 | 240 / sec | n/a | Engineering and maintenance |
| GIGe Vision | Gigabit Ethernet | 412.5 K/sec | 26.5 Meg/sec (16-bit words). | Alternate control downlink and data uplink |
There are several clock sources available from the LCB clock synthesizer hardware (U28). These clocks provide synchronization to specific areas of the Torrent hardware and firmware. The table below lists the clock name, the nominal frequency and their intended application.
| Clock Name | Frequency (Mhz) | Purpose |
|---|---|---|
| OCLK (internal) | 106.25 | LCB Oscillator used during LCB Initialization and in Master mode. |
| sync_in_clk (internal) | 39.84375 | Master clock input when in Slave mode. OCLK is shut down |
| BCLK (internal) | 106.25 (Master) / 39.84375 (Slave) | Clock source for the clock synthesizer. OCLK or sync_in_clk |
| SysClk (internal) | 106.25 | General logic, Wishbone bus clock |
| LCLK | 106.25 | Low jitter clock source for the GTP Transceiver (SFPDP comms) |
| PCLK | 159.375 | Memory. |
| DCLK | 79.6875 | AFE interface bridge logic. |
| TCLK | 39.84375 | AFE ADC data clock |
| MCLK | 39.84375 | Sync port communications and synchronization logic |
These clocks are derived from U28 (LMK03000) using the following register constants
| Clock Name | Phase detect Freq. (Mhz) | VCO Freq. (Mhz) | Divide by 'R' Value | VCO Divider Value | Divide by 'N' Value | Clock Divider Value |
|---|---|---|---|---|---|---|
| SysClk | 13.28125 | 1275 | 8 | 2 | 48 | 6 |
| LCLK | 13.28125 | 1275 | 8 | 2 | 48 | 6 |
| PCLK | 13.28125 | 1275 | 8 | 2 | 48 | 4 |
| DCLK | 13.28125 | 1275 | 8 | 2 | 48 | 8 |
| TCLK | 13.28125 | 1275 | 8 | 2 | 48 | 16 |
| MCLK | 13.28125 | 1275 | 8 | 2 | 48 | 16 |
For DHE Slave operation, where the BCLK frequency is 39.84375 MHz, the value of the Divide by 'R' value changes to 3. All other constants remain the same.
There are two clock sources available to provide the master OUTSYNC_CLK. The FPGA internally generated source and a source generated directly from the clock synthesizer hardware (U28). These clocks provide synchronization to the slave DHE systems. The table below lists the combinations available by writing to the SyncClkSelect attribute.
| Attribute value | OUTSYNC_CLK Source | FPGA SYNC CLK source | Attribute value | OUTSYNC_CLK Source | FPGA SYNC CLK source |
|---|---|---|---|---|---|
| 0x0 | U28 | U28 | 0x8 | Invalid state | Invalid state |
| 0x1 | FPGA | U28 | 0x9 | Invalid state | Invalid state |
| 0x2 | U28 | FPGA | 0xA | U28 | Disabled |
| 0x3 | FPGA | FPGA | 0xB | FPGA | Disabled |
| 0x4 | Disabled | U28 | 0xC | Disabled | Disabled |
| 0x5 | Invalid state | Invalid state | 0xD | Invalid state | Invalid state |
| 0x6 | Disabled | FPGA | 0xE | Invalid state | Invalid state |
| 0x7 | Invalid state | Invalid state | 0xF | Invalid state | Invalid state |
The LCB supports an engineering RS232 communication port for engineering use. The available commands (shown below) are prefixed with the 'plus' (+) character (0x2B) and completed with a 'Line Feed' character (0x0A). The standard format of 9600 Baud, 8 bits, no parity is supported. Upper or lower case characters are recognized. All address and data values must be expressed in hex. Fields must be separated by a space or tab character. Backspace clears the current command (although currently the display looks messy).
| First Field | Second Field | Third Field | Forth Field | Command description |
|---|---|---|---|---|
| +A | 16-bit vector (valid range 0x0 through 0xFFFF) | Not Used | Not used | Forces an Asynchronous Command to synchronize the communication channels after reset |
| +R | Module number (valid range 0x01 through 0xFF) | Module Address (valid range 0x0 through 0xFFFF) | Not used | Returns the 32-bit contents of the addressed register (in hex) |
| +W | Module number (valid range 0x01 through 0xFF) | Module address (valid range 0x0 through 0xFFFF) | 32-bit data value (valid range 0x0 through 0xFFFFFFFF) | Writes the 32-bit value to the addressed register |
| +S | 8-bit data value (valid range 0x0 through 0xFF) as sequencer start vector | Not used | Not used | Triggers a 'Start Exposure' event in the sequencer with the 8-bit start vector |
As per ICD 6.1 we use a board select code in each command sent to the LCB to address the individual modules that make up the firmware suit loaded to the Virtex part. This note pretends to fix the identity of the modules selected by each bit of the board select bit field used in the command structure. There are 10 bits available in this field. Torrent currently supports the use of the lowest order five bits although eight bits can be specified (with minor modification) in the Torrent architecture. The table below identifies the correspondence:
| Board Select Bit | Module Selected | Module Abbreviation | Module Identity Code | Module purpose |
|---|---|---|---|---|
| 0 (0x01) | LCB Control Module | LCB | 201 | Communications and digital control of the Torrent DHE |
| 1 (0x02) | Power Supply Services | PSM | 202 | Safety, Control, and telemetry of the power supply board (PSM) |
| 2 (0x04) | Configuration Services | CFG | 203 | Configuration data management (eeprom data), LCB clock control and sequencer (CFG) |
| 3 (0x08) | Pixel Data Services | PIX | 204 | Pixel data memory and descrambling logic common to OUV and IR (PIX) |
| 4 (0x10) | Analog Front End Control (AFE) | AFE | 205 | Analog front end electronics control and pixel acquisition (IR or OUV). |
| 5 (0x20) | Spare select bit | SPR1 | Not assigned | Spare module select bit. |
| 6 (0x40) | Spare select bit | SPR2 | Not assigned | Spare module select bit. |
| 7 (0x80) | Clock Services | CLK | 208 | Clock control module. |
The LCB_Control module supplies four duplex channels of communications with the DHE. These four comms channels are: Serial FPTP (Systran Emulation), GIGe (Gigabit ethernet), UART (via serial at 9600 Baud, no handshake), and the SYNC port that links to other slave/master DHE's. The comms destination bits set the required destination for these devices. Setting more than one bit results (mostly !) in parallel transmission to all devices.
| Bit Number | Comm Device |
|---|---|
| 0 ("0001") | Serial FPDP |
| 1 ("0010") | SYNC Port |
| 2 ("0100") | UART Port |
| 3 ("1000") | GIGe Port |
Each firmware module must supply several registers to support the automatic recognition and configuration processes of the PAN computer. These module addresses are shown below with their functional description:
| Address | Register Name | Write / Read | Register purpose |
|---|---|---|---|
| 0xFFFF | CodeId | 32-bit read only | Version number of the firmware module code as an integer. Divide by 100 for major / minor version. |
| 0xFFFF | RebootCmd | 32-bit Write only (data discarded) | Write to this register to warm reboot the LCB. All module select bits must be high i.e. 0xFF. |
| 0xFFFE | ModuleId | 32-bit read only | Module identification number of the firmware module - see section on Firmware Module Addressing and Identity Codes |
| 0xFFFE | ResetCmd | 32-bit Write only (data discarded) | Write to this register to reset the module. Multiple module select bits may be specified in the same command. Writing to this location with the all board select bits set high effects a general LCB system reset to all modules and the wishbone bus infrastructure. |
| 0xFFFD | Status | 32-bit Read only | Read of module status word - Data is module specific. |
The power supply monitors the state of the hardware protection circuits on the LCB-MEZ board. These status bits, when true, indicate a hardware protection fault condition that has interrupted the power supply to one or both of the AFE boards. This status regester is (usually) read as an attribute from the DHE at address 0x016F. The attribute name is PwrSupplyStatus.The status bits and their function definitions are shown below :
| Bit | Purpose | Bit | Purpose |
|---|---|---|---|
| 7 | AFE-1 VANA Power Protection Active | 3 | AFE-1 / AFE-2 VHV Power Protection Active |
| 6 | AFE-1 VCB Power Protection Active | 2 | Vbb supply active |
| 5 | AFE-2 VANA Power Protection Active | 1 | AFE Power Up Sequence Complete / AFE Power is _ON_ |
| 4 | AFE-2 VCB Power Protection Active | 0 | Power Supply Power Up Sequence Complete / Power is Available |
The mezzanine override register allows you to independently control the AFE power enable bits for the mezzanine board. This is _ONLY_ used for testing purposes since indiscriminate enabling power supplies can cause you to exceed the power supply load capabilities. This register is read and write at address 0x202 in the PSM module
| Bit | Purpose | Bit | Purpose |
|---|---|---|---|
| 7 | Not used | 3 | Not used |
| 6 | AFE 2 +/- VHV supply enable | 2 | AFE 1 +/- VHV supply enable |
| 5 | AFE 2 +/- VCB supply enable | 1 | AFE 1 +/- VCB supply enable |
| 4 | AFE 2 +/- VANA supply enable | 0 | AFE 1 +/- VANA supply enable |
This register select which temperature sensor in the DHE is to be used for feedback in the DHE temperature servo loop. The selection of the sensor is based upon a 1 Of 8 (3-bit) code set into the DheTempSensorSlct attribute. The codes are :
| Code | Selected Temp Sensor |
|---|---|
| 0 ("000") | FPGA temperature sensor (default) |
| 1 ("001") | LCB_temperature0 |
| 2 ("010") | LCB_temperature1 |
| 3 ("011") | AFE1_temperature0 |
| 4 ("100") | AFE1_temperature1 |
| 5 ("101") | AFE2_temperature0 |
| 6 ("110") | AFE2_temperature1 |
| 7 ("111") | Load feedback from PAN attribute write (for testing purposes) |
Each firmware module that requires to know the sequencer state information provides a 32-bit register at address 0xFFF0. The sequencer uses this register to periodically write the sequencer state information to all modules that use this address. The lower 16-bits of the register are static values and may be used to indicate the current mode of the sequencer function (e.g. ROI Readout Mode, Digital Averaging Enabled, etc.). The top 16-bits (31:16) are strobe signals that indicate an event during the sequencer operation (Frame Start, Line Start, etc.) and these bits persist for, and are synchronous to one SysClk cycle before being cancelled. The table below indicates the significance of the Sequencer State Register.
| Bit | Signal | Type | Used By | Bit | Signal | Type | Used By |
|---|---|---|---|---|---|---|---|
| 31 | FrameStartSync | Strobe | AFE | 15 | Spare | Static | n/a |
| 30 | LineStartSync | Strobe | AFE | 14 | Spare | Static | n/a |
| 29 | Spare | Strobe | n/a | 13 | Spare | Static | n/a |
| 28 | Spare | Strobe | n/a | 12 | Spare | Static | n/a |
| 27 | Spare | Strobe | n/a | 11 | Spare | Static | n/a |
| 26 | Spare | Strobe | n/a | 10 | Spare | Static | n/a |
| 25 | Spare | Strobe | n/a | 9 | Spare | Static | n/a |
| 24 | Spare | Strobe | n/a | 8 | Spare | Static | n/a |
| 23 | Spare | Strobe | n/a | 7 | Spare | Static | n/a |
| 22 | Spare | Strobe | n/a | 6 | Spare | Static | n/a |
| 21 | Spare | Strobe | n/a | 5 | Spare | Static | n/a |
| 20 | Spare | Strobe | n/a | 4 | Spare | Static | n/a |
| 19 | Spare | Strobe | n/a | 3 | Spare | Static | n/a |
| 18 | Spare | Strobe | n/a | 2 | Spare | Static | n/a |
| 17 | Spare | Strobe | n/a | 1 | Spare | Static | n/a |
| 16 | Spare | Strobe | n/a | 0 | Spare | Static | n/a |
There are five I2C buses associated with the Torrent DHE; one I2C bus for every physical board (LCB, PSM, TSM, AFE1, AFE2). There are four devices attached to each bus. This table lists their addresses and describes their use. During the DHE initialization (just after boot), the SDA signal line of each I2C bus is used to detect the presence of the physical board. The SCL signal for AFE1 (AFE_SCL_SRC0) is also used to direct the revision of the code that is booted at power up. This signal is pulled 'high' through a 50K Ohm pullup to 3.3v on the LCB. IR AFE boards should pull this signal low via a 3.3K Ohm resistor to the VPIFC GND return. This will select revision zero of the XF32P eeprom (LCB U43) boot code to load to the FPGA for IR operation. CCD AFE boards should leave this signal floating to select revision 1 of the boot code for VIS operation.
| Address | Device Type | Description |
|---|---|---|
| 0x48 | MCP9803 | Temperature sensor used to control the DHE operating temperature and supply telemetry |
| 0x49 | MCP9803 | Temperature sensor used to control the DHE operating temperature and supply telemetry |
| 0x50 | DS28CM00 | 48-bit silicon serial number as unique identity for each hardware board. Only the ls 32-bits are read. |
| 0x54 | 24AA128 | Calibration coefficient store space. Page written and read; 256 Pages each with 16 x 32-bit words. |
For PAN control of these resources there are several registers that are used to read and write to the I2C devices. These are listed in the following table:
| Attribute name | Address | Write Value | Read Value | Description |
|---|---|---|---|---|
| DetectI2CBus | 0x0012 | Anything |
Bit(4)=AFE2 Detected, Bit(3)=AFE1 Detected, Bit(2)=TSM Detected, Bit(1)=PSM Detected, Bits(0)=always '1' |
5-bit read/write register. Write anything to initiate I2C bus detection, Read to see hardware devices available |
| ReadI2CBusTemps | 0x0013 | Bits(20:16)=I2C Channel Addr, Bit(0)=Temperature sensor 1 or 2. | Not Accessible | 32-bit write register. Write to initiate I2C temperature sensor read cycle and update read only registers. |
|
ReadI2CBusSerial Numbers |
0x0014 | Bits(20:16)=I2C Channel Addr. | Not Accessible | 32-bit write register. Write to initiate I2C silicon serial number reads and update read only registers |
| eepRdCmdReg | 0x0020 | Bits(20:16)=I2C Channel Addr. Bits(7:0)=EEProm page address. |
Bit(31)=I2C manager busy, Bit(30)= Error occurred during read - bad I2C acknowledge. |
32-bit read/write register. Command register to select and read an eeprom page |
| eepWrtCmdReg | 0x0021 | Bits(20:16)=I2C Channel Addr. Bits(7:0)=EEProm page address. |
Bit(31)=I2C manager busy, Bit(30)= Error occurred during write - bad I2C acknowledge. |
32-bit read/write register. Command register to select and write an eeprom page |
Channel Address values for the physical hardware boards are: LCB = 1, PSM = 2, TSM = 4, AFE1 = 8, AFE2 = 16.
For the ReadI2CBusTemps, ReadI2CBusSerialNumbers, and eepWrtCmdReg commands, multiple channel addresses are allowed (i.e. you can read multiple temperature sensors or write the same data to multiple EEproms using just one command transaction).
For the eepRdCmdReg command, only one unique channel address is allowed.
There are two 8-bit registers assigned to provide visual indication of the internal signals of the FPGA. These registers are read / write. By setting a bit true the indicator (LED1 or LED2) will flash briefly (25ms) every time the selected signal becomes active true. LED1 is currently mounted on the Sync In port connector and LED2 is mounted on the Sync Out Port connector. The tables below indicate the significance of each attribute bit.
| bit | signal |
|---|---|
| 7 | BusReset |
| 6 | SlaveErrOut(4) |
| 5 | SlaveErrOut(3) |
| 4 | SlaveErrOut(2) |
| 3 | SlaveErrOut(1) |
| 2 | SlaveErrOut(0) |
| 1 | CfgCycleRequest |
| 0 | LcbCycRequest |
| bit | signal |
|---|---|
| 7 | SRC_SYNC_OUT |
| 6 | SNK_SYNC_IN |
| 5 | V33_SYNC_OUT |
| 4 | V300_POLARITY |
| 3 | V180_PWR_EN_N |
| 2 | V80_PWR_EN_N |
| 1 | VFAN_PWR_EN_N |
| 0 | MCLK_SEL_N |
This attribute controls the selection of a group of eight signals that are presented on the CFGDATA(7:0) signals (connector J4) on the LCB. By setting the attribute to different values, the hardware debug signals are available for diagnostic use. The attribute accepts values from zero to ten. The list below shows the significance.
| Value | Signal Group |
|---|---|
| 0 | Signals off |
| 1 | LCB Control Signal group |
| 2 | PSM Services Signal group |
| 3 | CFG Services Signal group |
| 4 | PIX Services Signal group |
| 5 | AFE Control Signal group |
| 6 | Signals off - Future AFE2 Signal group |
| 7 | Signals off - Spare |
| 8 | CLK Services Signal group |
| 9 | System Bus Signal group |
| 10 | Auxiliary Signal group |
These tables list the individual signals for each group.
| bit | signal |
|---|---|
| 7 | GIGe_PIXEL_CLK |
| 6 | GIGe_FVAL |
| 5 | GIGe_LVAL |
| 4 | GIGe_DVAL |
| 3 | PixDataRdy |
| 2 | GIGe_BULK0_CLK |
| 1 | GIGe_BULK0_RXD |
| 0 | LinkUp |
| bit | signal |
|---|---|
| 7 | AfePwrIsOn |
| 6 | TEMP_2_SNS |
| 5 | TEMP_1_SNS |
| 4 | LOGIC_SYNC |
| 3 | V300_SYNC |
| 2 | V180_SYNC |
| 1 | V80_SYNC |
| 0 | V33_SYNC |
| bit | signal |
|---|---|
| 7 | MstrScl |
| 6 | MstrSdain |
| 5 | MstrSdaOut(2) |
| 4 | MstrWrtEn |
| 3 | SYNC_DHE |
| 2 | SE_OUT |
| 1 | SE_READY |
| 0 | SYNC_POWER |
| bit | signal |
|---|---|
| 7 | MemInitDone |
| 6 | DlyClkLocked |
| 5 | app_af_wren |
| 4 | app_af_cmd(0) |
| 3 | app_af_cmd(1) |
| 2 | rd_data_valid |
| 1 | app_wdf_wre |
| 0 | MemoryDataClk |
| bit | signal |
|---|---|
| 7 | DacDevData(17) |
| 6 | DacDevData(16) |
| 5 | AFE_CLKBIAS(77) |
| 4 | AFE_CLKBIAS(48) |
| 3 | SerialSync(0) |
| 2 | SerialData(0) |
| 1 | SerialClk(0) |
| 0 | DacCtrlDataRdy |
| bit | signal |
|---|---|
| 7 | DCLK_FEED |
| 6 | BCLK_FEED |
| 5 | CLK_CTRL_CS_N |
| 4 | CLK_CTRL_GOE |
| 3 | CLK_CTRL_LOCK |
| 2 | CLK_CTRL_SYNC |
| 1 | CLK_CTRL_DATA |
| 0 | CLK_CTRL_CLK |
| bit | signal |
|---|---|
| 7 | Mstr1Grnt |
| 6 | Mstr0Grnt |
| 5 | SlaveCycle |
| 4 | SlaveWrite |
| 3 | SlaveError |
| 2 | StatusEnable |
| 1 | SlaveAck1 |
| 0 | SlaveAck0 |
Each firmware module can supply eight bits of 'out of band' status information which is used to transport slow signals (such as static configuration values) to other modules. The routing is controlled by the System Intercon module which employs static assignment to route input status bits to the global 32-bit output status sent to the other modules slave interface. The table below shows the routing information for the system at FPGA version level 2.22.
| Bit | Signal | Origin | Used By | Bit | Signal | Origin | Used By |
|---|---|---|---|---|---|---|---|
| 31 | ShutDownQuick | PSM | AFE | 15 | n/a | n/a | Spare |
| 30 | AsyncFlag | LCB | CFG | 14 | n/a | n/a | Spare |
| 29 | ReadoutInProgress | CFG | AFE | 13 | n/a | n/a | Spare |
| 28 | FrameStart | CFG | AFE | 12 | n/a | n/a | Spare |
| 27 | LineStart | CFG | AFE | 11 | n/a | n/a | Spare |
| 26 | MemPwrEnbld | PSM | PIX | 10 | n/a | n/a | Spare |
| 25 | ClocksAreLocked | CLK | PIX | 9 | n/a | n/a | Spare |
| 24 | AFEPowerOn | PSM | AFE | 8 | StreamMode | PIX | AFE |
| 23 | VHVPolarity | PSM | AFE | 7 | DheIsSlave | CFG | LCB, CLK |
| 22 | AFE 2 is enabled | AFE | PSM | 6 | Pixels16 | PIX | LCB |
| 21 | AFE 1 is enabled | AFE | PSM | 5 | PackedPixels | PIX | LCB |
| 20 | n/a | n/a | Spare | 4 | AFE2_Detected | CFG | PSM, AFE |
| 19 | n/a | n/a | Spare | 3 | AFE1_Detected | CFG | PSM, AFE |
| 18 | n/a | n/a | Spare | 2 | TempChanSlct(2) | PSM | CFG |
| 17 | n/a | n/a | Spare | 1 | TempChanSlct(1) | PSM | CFG |
| 16 | n/a | n/a | Spare | 0 | TempChanSlct(0) | PSM | CFG |
These next tables show the module status output assignments:
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 7 | n/a | Spare | 3 | n/a | Spare |
| 6 | n/a | Spare | 2 | n/a | Spare |
| 5 | n/a | Spare | 1 | n/a | Spare |
| 4 | n/a | Spare | 0 | AsyncFlag | True after reboot while waiting for a comm port async command |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 0 | AsyncFlag_i | Awaiting communication sync command from PAN | 7:1 | n/a | Spares |
| 8 | CommDeviceBusy_i | The science data comms channel is blocked up | 9 | SfpdpLossOfSig_i | Systran link down. No carrier present signal |
| 10 | SfpdpTxFault_i | There is a hardware fault in the Systran optical transmitter part | 11:12 | n/a | Spares |
| 28:13 | WbErrorStats_i(15:0) | Wishbone bus error statistics |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 7 | n/a | Spare | 3 | ShutDownQuick | Emergency shutdown signal |
| 6 | VHVPolarity | True indicates N-Channel mode (positive VHV) | 2 | TempChanSlct(2) | 1 of 8 slct of DHE temperature control sensor |
| 5 | AFEPowerOn | The AFE boards have VANA+/- powered up | 1 | TempChanSlct(1) | 1 of 8 slct of DHE temperature control sensor |
| 4 | MemPwrEnbld | 1.8v Memory power is available. | 0 | TempChanSlct(0) | 1 of 8 slct of DHE temperature control sensor |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 0 | VFanTempSensorSlct_reg(0) | Same signal as system status | 1 | VFanTempSensorSlct_reg(1) | Same signal as system status |
| 2 | VFanTempSensorSlct_reg(2) | Same signal as system status | 3 | ShutDownQuick | Panic !! |
| 4 | TsmPresent_i | Indicates that the TSM is present. | 5 | n/a | Spare |
| 6 | n/a | Spare | 7 | n/a | Spare |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 0 | PrimaryPwrStat | Primary power is available | 1 | AfePwrStat | AFE power is available |
| 2 | VbbEnableFlag | Vbb supply is enabled (after safety conditioning) | 3 | AfeV300Fail | Mezzanine Fail indicator for VHV |
| 4 | Afe2V180Fail | Mezzanine Fail indicator for VCB on AFE2 | 5 | Afe2V80Fail | Mezzanine Fail indicator for VANA on AFE2 |
| 6 | Afe1V180Fail | Mezzanine Fail indicator for VCB on AFE1 | 7 | Afe1V80Fail | Mezzanine Fail indicator for VANA on AFE1 |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 7:0 | MezOverRide_reg | As written by PAN | 8 | Afe1V80Fail | Mezzanine Fail indicator for VANA on AFE1 |
| 9 | Afe1V180Fail | Mezzanine Fail indicator for VCB on AFE1 | 10 | AfeV300Fail | Mezzanine Fail indicator for VHV |
| 11 | n/a | Not used | 12 | Afe2V80Fail | Mezzanine Fail indicator for VANA on AFE2 |
| 13 | Afe2V180Fail | Mezzanine Fail indicator for VCB on AFE2 | 14 | AfeV300Fail | Repeat of Mezzanine Fail indicator for VHV |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 7 | n/a | Spare | 3 | DheIsSlave | The DHE is configured as a slave device in a multi-DHE system |
| 6 | n/a | Spare | 2 | AFE2_Detected | The AFE2 board is physically present |
| 5 | LineStart | Indicates a new row beginning | 1 | AFE1_Detected | The AFE1 board is physically present |
| 4 | FrameStart | Indicates a new frame beginning | 0 | ReadoutInProgress | Sequencer is actively reading detector |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 0 | ReadoutActive | Sequencer EFR bit to indicate that ... | 1 | AFE0_ModuleDetect | AFE1 has been detected during the I2C bus search |
| 2 | AFE1_ModuleDetect | AFE2 has been detected during the I2C bus search | 3 | DheIsSlave | DHE is operating as a slave DHE |
| 4 | FrameStart | A frame start flag has been issued in the pixel stream | 5 | LineStart | A line start flag has been issued in the pixel stream |
| 15:6 | not used | Spare | 19:16 | BusTimeoutReg | Sequencer Wishbone master Bus Timeout Register |
| 23:20 | BusGrantReg | Sequencer Wishbone master Bus Grant error register | 27:24 | BusErrorReg | Sequencer Wishbone master Bus slave Error register |
| 31:28 | BusEventStatusReg | Sequencer Wishbone master Bus status register |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 7 | n/a | Spare | 3 | n/a | Spare |
| 6 | n/a | Spare | 2 | StreamMode | Pixel data path configured for Stream Data acquisition mode i.e. no memory buffering |
| 5 | n/a | Spare | 1 | Pixels16 | Pixel data has been scaled to 16-bits by the PIX module. |
| 4 | n/a | Spare | 0 | PackedPixels | Each 32-bit pixel data word contains 2 x 16-bit pixels. |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 0 | MemCntrInitDone_i | Memory system calibrated and ready for use | 31:1 | n/a | Spares |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 7 | n/a | Spare | 3 | n/a | Spare |
| 6 | n/a | Spare | 2 | n/a | Spare |
| 5 | n/a | Spare | 1 | afe_enbl_reg(1) | True when AFE 2 is enabled via AfeInterfaceEnbl |
| 4 | n/a | Spare | 0 | afe_enbl_reg(0) | True when AFE 1 is enabled via AfeInterfaceEnbl |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 0 | RfshTpActFlag | Test points are being refreshed | 1 | RfshActiveFlag | DAC and Test Points are being refreshed |
| 4 | tp_fifo_empty | The Test point write FIFO is empty | 5 | dac_fifo_empty | The DAC write FIFO is empty |
| 8 | TelScanGo | Telemetry scan is active | 9 | RfshTpWrtFifo | transfer test point index to tp write fifo |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 7 | n/a | Spare | 3 | n/a | Spare |
| 6 | n/a | Spare | 2 | n/a | Spare |
| 5 | n/a | Spare | 1 | n/a | Spare |
| 4 | n/a | Spare | 0 | ClocksAreLocked | Clock Synthesizer has lock and clocks are good |
| Bit | Signal | Description | Bit | Signal | Description |
|---|---|---|---|---|---|
| 0 | LockDetect_i | The clock generator is running locked to the reference frequency | 31:1 | n/a | Spares |
1) Point the Impact tool to the systemBuildFilename.ipf tool by right clicking the "Configure Target Device"/"Properties" menu item.
2) Load Impact and confirm that the boundary scan devices have the correct file associations, systemBuildFilename.mcs and systemBuildFilename.bit.
3) Right click the xcf32p device and select "Programming Properties". Make sure the following boxes are checked:
All other check boxes should be clear
4) Right click on the xcf32p device, select "Load Configuration Revision", and set to 0.
5) Right click on the xcf32p device, select "Set Erase Properties", and set to Erase Entire Device.
6) Right click on the xcf32p device and select "Program" to program the device. This operation will take a few minutes.
This is the procedure to create the PROM MCS file from the FPGA BIT file.
1) In the "Processes" window of the Xilinx ISE project navagator, click on "Configure Target Device" and then double click "Generate Target PROM/ACE File. This will start the Impact tool and display a Welcome page.
2) Select "Prepare a PROM File" and clock Next.
3) A new page is displayed to prepare the PROM files. Set the following:
Click next.
4) Select the PROM mode page - set the following:
Click next.
5) Specify Xilinx PROM Device page - set the following:
Click next.
6) A file generation summary is displayed - click finish.
7) The PROM file formatter is launched and a pop-up to start adding device file to Revision:0 is displayed. Click OK.
8) The files in the project location directory are displayed. Select the appropriate BIT file and click OPEN.
9) Another pop-up appears Would you like to add another design file to Revision 0:? Click NO
10) Another pop-up appears Start adding device file to Revision:1. Click OK.
11) The files in the project location directory are displayed again. Select the same BIT file as in step 8 and click OPEN.
12) Another pop-up appears Would you like to add another design file to Revision 1:? Click NO.
13) Another pop-up appears You have completed the device file entry - click OK.
14) In the "Configuration Operations" tab of the ISE Navigator double-click on the Generate File operation. This will complete the process and a window should pop-up indicating that it succeeded.
Mechanical Parts
TRNT-EL-02-1001 CARD GUIDE MOUNT [555]
TRNT-EL-02-1002 CONTROLLER BOTTOM PLATE [556]
TRNT-EL-02-1003B CONTROLLER REAR PANEL [557]
TRNT-EL-02-1004A CONTROLLER FRONT PANEL [558]
TRNT-EL-02-1005 CONTROLLER CROSS RAIL RIGHT [559]
TRNT-EL-02-1006 CONTROLLER CROSS RAIL LEFT [560]
TRNT-EL-02-1007B CONTROLLER REAR PANEL INSERT [561]
TRNT-EL-02-1008B CONTROLLER COVER [562]
TRNT-EL-02-1010B PSM ENCLOSURE BASE [563]
TRNT-EL-02-1011 PSM ENCLOSURE BOTTOM COVER [564]
TRNT-EL-02-1012A PSM ENCLOSURE FILL PLATE [565]
TRNT-EL-02-1013 CONTROLLER SUPPORT RAIL SPACER [566]
TRNT-EL-02-1016 CONTROLLER PCB SUPPORT RAIL REAR [567]CON
TRNT-EL-02-1017 CONTROLLER PCB SUPPORT RAIL FRONT [568]
TRNT-EL-02-1019A CONTROLLER EMI PLATE [569]
TRNT-EL-02-1020 DHE MOUNTING TAB [570]
TRNT-EL-02-1021B TRANSITION MODULE BASE PLATE [571]
TRNT-EL-02-1022B TRANSITION MODULE ISOLATION CONNECTOR PLATE [572]
TRNT-EL-02-1023C TRANSITION MODULE ISOLATION RAIL [573]
TRNT-EL-02-1024A TRANSITION MODULE BASE HEADER [574]
TRNT-EL-02-1025B TRANSITION MODULE SIDE PLATE, LEFT [575]
TRNT-EL-02-1026B TRANSITION MODULE SIDE PLATE, RIGHT [576]
TRNT-EL-02-1027A TRANSITION MODULE UTILITY BOARD HEADER [577]
TRNT-EL-02-1028B TRANSITION MODULE BASE TOP COVER PLATE TAB [578]
TRNT-EL-02-1029A TRANSITION MODULE BASE FRONT COVER [579]
TRNT-EL-02-1030A TRANSITION MODULE BASE TOP COVER [580]
TRNT-EL-02-1031 ETHERNET BOARD STANDOFF [581]
TRNT-EL-02-1032 ETHERNET BOARD COVER [582]
TRNT-EL-02-1034B Hex Jam Nut .688-24 [583]
TRNT-EL-02-1035B Hex Jam Nut 1.063-18 [584]
TRNT-EL-02-1036A Hex Jam Nut 1.188-18 [585]
TRNT-EL-02-1037A FINNED BLWR HSG [586]
TRNT-EL-02-1038 HSG CVR [587]
These documents outline assembly procedures for constructing the Torrent DHE. They are specifically applicable to techniques used at NOIRLabs but presented here as a help to understanding the assembly process associated with the various mechanical and electrical modules.
Parts Kit Documents
TRNT-EL-02-0000 Blank Dewar Interface kit [588] Rev -0D-
TRNT-EL-02-0014 Transition Module Base Kit [589] Rev -0D-
TRNT-EL-02-0015 KPNO Dewar Connector Plate Kit [590] Rev -0D-
TRNT-EL-02-0016 CCD Flex Cable Kit [591] Rev -0D-
TRNT-EL-02-0017 LCB Kit [592] Rev -0D-
TRNT-EL-02-0018 Controller Base Kit [593] Rev -0D-
TRNT-EL-02-0020 External Connector Kit [594] Rev -0D-
TRNT-EL-02-0021 TSM Covers Kit [595] Rev -0D-
TRNT-EL-02-0022 Controller Cover Kit [596] Rev -0D-
Assembly Documents
TRNT-EL-02-0001A DETECTOR HEAD ELECTRONICS [597]
TRNT-EL-02-0002B CONTROLLER ASSEMBLY [598]
TRNT-EL-02-0003C TRANSITION MODULE ASSEMBLY [599]
TRNT-EL-02-0004B POWER SUPPLY MODULE [600]
TRNT-EL-02-0005A CCD PREAMP TRANSITION BOARD [601]
TRNT-EL-02-0006B TRANSITION MODULE CHASSIS [602]
TRNT-EL-02-0007B BLOWER HOUSING [603]
TRNT-EL-02-0008A CONTROLLER MODULE CHASSIS [604]
TRNT-EL-02-0009 CONTROLLER MODULE PCB MOUNT REAR [605]
TRNT-EL-02-0010 CONTROLLER MODULE PCB MOUNT FRONT [606]
TRNT-EL-02-0011A ETHERNET BOARD ASSEMBLY [607]
TRNT-EL-02-0012B LCB ASSEMBLY [608]
TRNT-EL-02-0024 Torrent Assembly Steps - Controller Module [609] Rev -A-
TRNT-EL-02-0025 TRAN ISOL PLT [610]
TRNT-EL-02-0026 AFE EXT BRD ASSY [611]
TRNT-TS-01-0002 Board Test Requirements [612] Rev 2
ECOFORM TEMPLATE [613]
Master ECO List [614]
TRNT-001 [615]
TRNT-002 [616]
TRNT-003 [617]
TRNT-004 [618]
TRNT-005 [619]
TRNT-006 [620]
TRNT-007 [621]
TRNT-008 [622]
TRNT-009 [623]
TRNT-010 [624]
TRNT-011 [625]
TRNT-012 [626]
TRNT-013 [627]
TRNT-014 [628]
TRNT-015 [629]
TRNT-016 [630]
TRNT-017 [631]
TRNT-018 [632]
TRNT-019 [633]
TRNT-020 [634]
TRNT-021 [635]
TRNT-022 [636]
TRNT-024 [637]
TRNT-025 [638]
TRNT-026 [639]
TRNT-027 [640]
TRNT-028 [641]
TRNT-029 [642]
TRNT-030 [643]
TRNT-031 [644]
TRNT-033 [645]
TRNT-034 [646]
TRNT-035 [647]
TRNT-036 [648]
TRNT-037 [649]
TRNT-038 [650]
TRNT-039 [651]
TRNT-040 [652]
TRNT-041 [653]
These system configuration data packages can be used as templates for future instrument configuration sets. They are offered 'as is' without any warranty as to their operational state or suitability of purpose to other implementations.
Configuration _basicCCD [654] - Test configuration for the Borg tool
Configuration _bill [655] - Laboratory system which always works
Configuration _chile1 [656] - Used to characterize and test the prototype Torrent DHE against the requirements document
Configuration _chiron [657] - Operational configuration running an E2V 4k x 4k detector on the Chiron spectrograph
Here is a list of current MONSOON systems in use and the facilities employing MONSOON technology.
 |
KPNO |
Kitt Peak - Ohio State Multi-Object Spectrograph (KOSMOS) |
||
|
NOAO Extemely Wide-field Infrared iMager (NEWFIRM) |
||||
|
MOSAIC 1.1 Wide Field Imager |
||||
|
2.1 meter Telescope Imager T2KA (CFIM) |
||||
|
CTIO |
CHIRON: fiber echelle at CTIO 1.5-m telescope CTIO - Ohio State Multi-Object Spectrograph (COSMOS) SMARTS - 0.9Mtr Imager |
||
 |
Fermilab Fermi National Accelerator Laboratory |
Dark Energy Camera (DECam) |
||
|
Dark Matter In CCDs (DAMIC) www.fnal.gov/pub/today/archive_2009/today09-04-08.html [667] |
||||
 |
UIUC University of Illinois at Urbana-Champaign |
DECam Partner MONSOON Software and Hardware Design Collaborator |
||
 |
IFAE |
DECam Partner MONSOON Software and Hardware Design Collaborator |
||
 |
Ciemat |
DECam Partner MONSOON Software and Hardware Design Collaborator |
||
 |
University of Wisconsin |
WIYN High-resolution InfraRed Camera (WHIRC) |
||
 |
Indiana |
FHIRE and FHIRE-II |
||
 |
WIYN www.noao.edu/wiyn [675] |
Bench Spectrograph Detector Upgrade - 2.6kx4k 2 Output CCD |
||
|
QUOTA 32 Channel QUad OTA CCD |
||||
 |
INSTITUT DE CIÈNCIES DE L'ESPAI |
Physics of the accelerating Universe (PAU) |
||
 |
CfAI |
MONSOON Firmware Development Collaborator |
||
 |
Fishcamp Engineering |
MONSOON Hardware and Firmware Development Collaborator |
||
Links
[1] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/MNSN_DataSheet_Rev1.1.pdf
[2] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/TRNT_DataSheet_Rev%2041.pdf
[3] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/What_is_MONSOON/MonsoonApplicationsPresentation.pdf
[4] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/What_is_MONSOON/IntroductionToMonsoon.pdf
[5] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Papers/5496-41.pdf
[6] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Papers/5496-42.pdf
[7] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Papers/5496-20.pdf
[8] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Papers/5496-43.pdf
[9] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Papers/5499-55.pdf
[10] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/review01.pdf
[11] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/review02.pdf
[12] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/review03.pdf
[13] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/review04.ppt
[14] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/review05.pdf
[15] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/obs_council.pdf
[16] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/TRNT_Introduction.pdf
[17] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/TRNT_Electronics_1.pdf
[18] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/TRNT_Electronics_2.pdf
[19] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/TRNT_Software.pdf
[20] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/TRNT_Mechanical.pdf
[21] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/TRNT_Manufacture.pdf
[22] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Presentations/KOSMOS.pdf
[23] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Licensing/The%20case%20for%20MONSOON%20Open%20Source%20development.pdf
[24] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Licensing/MONSOON_Availability_Public_Release_20040617.pdf
[25] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Licensing/Monsoon_License_Rev_1.0.pdf
[26] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/MNSN-AD-10-0001_Document_Structure.pdf
[27] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/TRNT-AD-10-0001_Document_Structure.pdf
[28] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/MNSN-AD-01-0004_ICD_6.0_Generic_DHE_Interface_Description_Rev_1.0.pdf
[29] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/MNSN-AD-01-0005_ICD_6.1_DHE_Interface_Description_Rev_1.1.pdf
[30] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/MNSN-AD-01-0002_ICD_4.0_Generic_Pixel_Service_Communications_Command_Response_and_Data_Stream_Interface_Description_Rev_1.1.pdf
[31] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/MNSN-AD-01-0003_ICD_5.0_PAN_Communications_Command_Response_and_Data_Stream_Interface_Description_Rev_1.0.pdf
[32] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Interface_Control_Documents/MNSN-AD-01-0007_ICD_5.1_PAN_Run-time_Configuration_Setup_and_Operating_Mode_Definition_Interface_Description_Rev_1.0.pdf
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[129] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/DECAM/Hardware/Crate_Wiring/DESDOC_2328-v33_Production_DHE_Crate_Wiring_Rev3.0%20V2.pdf
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[132] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/DECAM/Hardware/Crate_Wiring/DESDOC_2328-v33_Production_ICC_Cables%26Connectors_BOM_Version_PROD_ICC_REV2_0.xls
[133] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/DECAM/Hardware/Crate_Wiring/DESDOC_2328-v33_Production_Cooling_Fan_Plenum_Connections_Type1_and_Type22.pdf
[134] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/DECAM/Hardware/Crate_Wiring/DESDOC_2328-v33_Production_Power_Supply_Module_Connections_Type1_and_Type2.pdf
[135] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/DECAM/Hardware/Crate_Wiring/DESDOC_5740-v1_AC_Power_Cord_Specification.pdf
[136] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/DECAM/Hardware/Crate_Wiring/DESDOC_5739-v1_Grounding_Braid.pdf
[137] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/DECAM/Hardware/Crate_Wiring/DESDOC_1154-v9_Analog_Backplane_Connectors_V9.pdf
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[432] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/SystemConfig/_clkBrdTest.zip
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[438] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/SystemConfig/_mosaic1.zip
[439] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/SystemConfig/_NEWFIRM_Tucson.zip
[440] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/SystemConfig/_ota.zip
[441] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/SystemConfig/_pcmTest.zip
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[444] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/SystemConfig/_quota_guide.zip
[445] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Orange/SystemConfig/_tom.zip
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[454] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Torrent_User_Survey_Rev4.pdf
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[460] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-EL-04-1002_rB_Fab.pdf
[461] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-EL-04-2002_rB_Sch.pdf
[462] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/NOAO_TRNT_3002.zip
[463] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-EL-04-4002_rB_PrtLst.pdf
[464] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/torrentfpga_ver222.bit
[465] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TorrentFpga_Ver222.mcs
[466] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB/TRNT-TS-01-0003_LCB_Test_Procedure_rev_0.pdf
[467] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-0003_rA3_asbly.pdf
[468] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-1003_rA.pdf
[469] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-2003_rA4_Sch.pdf
[470] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-3003_rA_layout.pdf
[471] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/LCB-MEZ/TRNT-EL-04-4003_rA5_PrtLst.pdf
[472] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-0001_rB_PSB_Asbly.pdf
[473] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-1001_rB_PSB_FabDetail.pdf
[474] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-2001_rB_PSB_Sch.pdf
[475] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-3001_PSB.zip
[476] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/PSM/TRNT-EL-04-4001_rB_PrtLst.pdf
[477] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-0004_rC_AFE_AsblyDwgl.pdf
[478] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-1004_rC_AFE_FabDetail.pdf
[479] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-2004_rC1_AFE_Sch.pdf
[480] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-3004_rC_AFE_Artwk.pdf
[481] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-4004_rC1_PrtLst.pdf
[482] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/AFE_Calibration_Worksheets.xls
[483] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-0008_rOD.pdf
[484] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-1008_rOD.pdf
[485] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-2008_rOD_Sch.pdf
[486] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-EL-04-3008_rOD.pdf
[487] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/AFE-CCD/TRNT-TS-01-0004_AFE-CCD_Test_Procedure_Rev_0.pdf
[488] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-0007_rC1_asby.pdf
[489] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-1007_rC_fab.pdf
[490] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-2007_rC1_Sch.pdf
[491] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-4007_rC1.xls
[492] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-0007_rB_Asby.pdf
[493] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-1007_rB_FabDetl.pdf
[494] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-2007_rB1_Sch.pdf
[495] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-3007_rB_artwork.pdf
[496] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-4007_rB2_PrtLst.pdf
[497] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-0009_rA1_Asbly.pdf
[498] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-1009_rA_fab.pdf
[499] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-2009_rA2_SCH.pdf
[500] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-3009_rA.pdf
[501] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/NOAO-TRNT-1009.zip
[502] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-EL-04-4009_rA4_PrtLst.pdf
[503] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/TSM-CCD/TRNT-TS-01-0005_TSM-UTIL_Test_Procedure_Rev_0.pdf
[504] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-0005_rA_Asbly.PDF
[505] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-1005_rA_Fab.PDF
[506] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-2005_rA_Sch.PDF
[507] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/NOAO-TRNT-1005_rA.zip
[508] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-0006_rA_Asbly.pdf
[509] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-1006_rA_Fab.pdf
[510] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-2006_rA_Sch.pdf
[511] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/FLEX/TRNT-EL-04-3006_rA_Artwk.pdf
[512] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0001_CablePSM-util.pdf
[513] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0002_CableShutter_Preflash.pdf
[514] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0003_Ethernet_Shld_wire.pdf
[515] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Hardware/CABLES/TRNT-EL-03-0006_TSM%20Chassis%20GND%20Wire.pdf
[516] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/MNSN-AD-08-0005_MONSOON_Software_Setup_Rev_2.1.pdf
[517] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0001%20Software%20System%20Description%20Rev%200.pdf
[518] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0002%20borg%20R0.pdf
[519] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0006%20Software%20User%20Manual%20R0.pdf
[520] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0003%20Assimilate%20Rev1.2.pdf
[521] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0004_Torrent_Collector_Rev_1.1.pdf
[522] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT-AD-08-0012%20Torrent%20Sequencer%20Description%20R0.pdf
[523] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Software/TRNT_Assembler_Ver_6.zip
[524] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Combined_Attribute_declarations_ver2.22_Rev2.pdf
[525] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/TRNT-AD-08-0011%20AFE%20Control%20Module%20Firmware%20R0.pdf
[526] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Torrent%20LCB%20Firmware%20Design%20Rev%20C3.pdf
[527] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/WishBone%20Bus%20Specification%20From%20OpenCores%20wbspec_b3-1.pdf
[528] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Clock%20Generation%20WorkBookV4%20.xls
[529] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/AFE%20Serial%20device%20control%20list.xls
[530] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PowerSupplySyncAnalysis.xls
[531] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/TorrentFpga_Ver222.zip
[532] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/AFE_Control_Ver221.zip
[533] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CFG_Services_Ver220.zip
[534] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CLK_Services_Ver221.zip
[535] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/DummyModule_V220.zip
[536] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/LCB_Control_Ver222.zip
[537] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PIX_Services_Ver221.zip
[538] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PSM_Services_Ver221.zip
[539] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CmdDecodeFifo.zip
[540] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/CommsDemuxPixBuffr_V106.zip
[541] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/I2C_InterfaceV100.zip
[542] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/I2C_Interface_V210.zip
[543] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/PixDataMuxFifo_V103.zip
[544] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SeqPatMemCore.zip
[545] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SeqProgMemCore.zip
[546] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SerialFPDP_fifo_5v5.zip
[547] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/SyncPortFifo_V100.zip
[548] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Uart_8.zip
[549] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/UartFifo.zip
[550] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/VideoFifo.zip
[551] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/Intercon_Ver222.zip
[552] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/WishBoneMasterInterfaceV106.zip
[553] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/WishBoneSlaveInterface_Ver207.zip
[554] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Firmware/NOAO_tblock.zip
[555] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1001%20CARD%20GUIDE%20MOUNT.pdf
[556] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1002%20CONTROLLER%20BOTTOM%20PLATE.pdf
[557] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1003B%20CONTROLLER%20REAR%20PANEL.pdf
[558] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1004A%20CONTROLLER%20FRONT%20PANEL.pdf
[559] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1005%20CONTROLLER%20CROSS%20RAIL%20RIGHT.pdf
[560] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1006%20CONTROLLER%20CROSS%20RAIL%20LEFT.pdf
[561] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1007B%20CONTROLLER%20REAR%20PANEL%20INSERT.PDF
[562] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1008B%20CONTROLLER%20COVER.pdf
[563] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1010B%20PSM%20ENCLOSURE%20BASE.PDF
[564] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1011%20PSM%20ENCLOSURE%20BOTTOM%20COVER.pdf
[565] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1012A%20PSM%20ENCLOSURE%20FILL%20PLATE.pdf
[566] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1013%20CONTROLLER%20SUPPORT%20RAIL%20SPACER.pdf
[567] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1016%20CONTROLLER%20PCB%20SUPPORT%20RAIL%20REAR.PDF
[568] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1017%20CONTROLLER%20PCB%20SUPPORT%20RAIL%20FRONT.PDF
[569] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1019A%20CONTROLLER%20EMI%20PLATE.pdf
[570] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1020%20DHE%20MOUNTING%20TAB.PDF
[571] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1021B%20TRANSITION%20MODULE%20BASE%20PLATE.pdf
[572] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1022B%20TRANSITION%20MODULE%20ISOLATION%20CONNECTOR%20PLATE.pdf
[573] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1023C%20TRANSITION%20MODULE%20ISOLATION%20RAIL.pdf
[574] http://www.ctio.noao.edu/noao/sites/default/files/instruments/Controllers/MONSOON/Technical_Documents/Torrent/Mechanical/TRNT-EL-02-1024A%20TRANSITION%20MODULE%20BASE%20HEADER.pdf
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